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Table 2-12. External Memory Interfaces/General Purpose Memory Controller Signals
Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
G17
ZCZ BALL [4]
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
gpmc_a9
gpmc_ad0
gpmc_ad1
GPMC Address
O
G18, U16
T16
GPMC Address
O
NA
GPMC Address
O
NA
V17
GPMC Address
O
U17, V2
W2
R4, T13, T14
R14, T1
T2, V15
T3, U15
T15, T4
U5, V16
R5, U16
U7
GPMC Address
O
GPMC Address
O
W3
GPMC Address
O
V3
GPMC Address
O
U3
GPMC Address
O
U7
GPMC Address
O
T7
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address Valid / Address Latch Enable
GPMC Byte Enable 0 / Command Latch Enable
GPMC Byte Enable 1
GPMC Clock
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
W10
V9
V7
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_advn_ale
gpmc_be0n_cle
gpmc_be1n
gpmc_clk
T12
U12
U13
T13
W17
V17
V12
W13
V13
W14
U14
W15
V15
W16
V10
V8
T11
U12
T12
R12
V13
U13
R8
T8
U8
V8
R9
T9
U10
T10
R7
O
T6
O
U15, V18
V14, V16
W8
U18, V9
U9, V12
V6
I/O
O
gpmc_csn0
gpmc_csn1
gpmc_csn2
gpmc_csn3
gpmc_csn4
gpmc_csn5
gpmc_csn6
gpmc_dir
GPMC Chip Select
GPMC Chip Select
O
V14
U15
U17
R15
W18
V18
V18
W9
U9
GPMC Chip Select
O
V9
GPMC Chip Select
O
T13
GPMC Chip Select
O
T17
GPMC Chip Select
O
U17
GPMC Chip Select
O
U18
GPMC Data Direction
GPMC Output / Read Enable
GPMC Wait 0
O
U18
gpmc_oen_ren
gpmc_wait0
gpmc_wait1
gpmc_wen
gpmc_wpn
O
T7
I
R15
V16
U8
T17
GPMC Wait 1
I
V12
GPMC Write Enable
GPMC Write Protect
O
U6
O
W18
U17
56
Terminal Description
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