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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
Table 2-11. External Memory Interfaces/DDR Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
N3
ddr_d4
ddr_d5
ddr_d6
ddr_d7
ddr_d8
ddr_d9
ddr_dqm0
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
I/O
P3
I/O
I/O
I/O
I/O
I/O
O
T1
T2
R3
K2
K1
N3
N4
P3
P4
J1
K1
M2
DDR WRITE ENABLE / DATA MASK FOR
DATA[7:0]
ddr_dqm1
ddr_dqs0
ddr_dqs1
ddr_dqsn0
ddr_dqsn1
DDR WRITE ENABLE / DATA MASK FOR
DATA[15:8]
O
K3
R1
L1
R2
L2
J2
P1
L1
P2
L2
DDR DATA STROBE FOR DATA[7:0]
(Differential+)
I/O
I/O
I/O
I/O
DDR DATA STROBE FOR DATA[15:8]
(Differential+)
DDR DATA STROBE FOR DATA[7:0]
(Differential-)
DDR DATA STROBE FOR DATA[15:8]
(Differential-)
ddr_nck
ddr_odt
ddr_rasn
DDR SDRAM CLOCK OUTPUT (Differential-)
ODT OUTPUT
O
O
O
C1
G1
F2
D1
G1
G4
DDR SDRAM ROW ADDRESS STROBE
OUTPUT (ACTIVE LOW)
ddr_resetn
ddr_vref
ddr_vtp
DDR3/DDR3L RESET OUTPUT (ACTIVE LOW)
Voltage Reference Input
O
A
I
G2
H4
J1
G2
J4
VTP Compensation Resistor
J3
ddr_wen
DDR SDRAM WRITE ENABLE OUTPUT
(ACTIVE LOW)
O
A4
B2
Table 2-12. External Memory Interfaces/General Purpose Memory Controller Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
U1
ZCZ BALL [4]
gpmc_a0
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
R1, R13
R2, U5, V14
T16, V5
R6, V17
U1
gpmc_a1
U2, U7
W5
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
gpmc_a2
W7
V4
W4
U2
U5
U3
V5
U4
V6
R13, V2
V14, V3
U14, V4
T14, T5
R3, R5, U14
F17, R14
F18, V15
G15, U15
G16, T15
G17, V16
U6
W6
V7
T7, V1
H19
H18
H17
G18
G19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
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