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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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2.3.1 External Memory Interfaces
Table 2-11. External Memory Interfaces/DDR Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
F3
ZCZ BALL [4]
ddr_a0
ddr_a1
ddr_a10
ddr_a11
ddr_a12
ddr_a13
ddr_a14
ddr_a15
ddr_a2
ddr_a3
ddr_a4
ddr_a5
ddr_a6
ddr_a7
ddr_a8
ddr_a9
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
O
F3
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
J2
H1
F4
F2
E3
H3
H4
D3
E4
C3
C2
B1
D5
E2
D4
C1
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
E2
G4
F4
H1
H3
E3
D1
B3
E5
A2
B1
D2
C3
B2
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
ddr_ba0
ddr_ba1
ddr_ba2
ddr_casn
DDR SDRAM BANK ADDRESS OUTPUT
DDR SDRAM BANK ADDRESS OUTPUT
DDR SDRAM BANK ADDRESS OUTPUT
O
O
O
O
A3
E1
B4
F1
C4
E1
B3
F1
DDR SDRAM COLUMN ADDRESS STROBE
OUTPUT (ACTIVE LOW)
ddr_ck
DDR SDRAM CLOCK OUTPUT (Differential+)
DDR SDRAM CLOCK ENABLE OUTPUT
DDR SDRAM CHIP SELECT OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
O
C2
G3
H2
N4
P4
M3
M4
M2
M1
N2
N1
P2
P1
D2
G3
H2
M3
M4
K2
K3
K4
L3
ddr_cke
ddr_csn0
ddr_d0
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ddr_d1
ddr_d10
ddr_d11
ddr_d12
ddr_d13
ddr_d14
ddr_d15
ddr_d2
L4
M1
N1
N2
ddr_d3
54
Terminal Description
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