AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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1-Bit, 4-Bit and 8-Bit MMC, SD, and SDIO
Modes
MMCSD0 has dedicated Power Rail for
1.8-V or 3.3-V Operation
Up to 48-MHz Data Transfer Rate
Supports Card Detect and Write Protect
Complies with MMC4.3 and SD and SDIO
2.0 Specifications
a Firmware Timer
512-Word Deep Internal FIFO
Supported Display Types:
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Character Displays - Uses LCD
Interface Display Driver (LIDD)
Controller to Program these Displays
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Passive Matrix LCD Displays - Uses
LCD Raster Display Controller to
Provide Timing and Data for Constant
Graphics Refresh to a Passive Display
Active Matrix LCD Displays - Uses
External Frame Buffer Space and the
Internal DMA Engine to Drive
– Up to Three I2C Master and Slave Interfaces
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Standard Mode (up to 100 kHz)
Fast Mode (up to 400 kHz)
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– Up to Four Banks of General-Purpose IO
(GPIO)
Streaming Data to the Panel
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32 GPIOs per Bank (Multiplexed with
Other Functional Pins)
– 12-Bit Successive Approximation Register
(SAR) ADC
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GPIOs Can be Used as Interrupt Inputs
(Up to Two Interrupt Inputs per Bank)
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200K Samples per Second
Input Can be Selected from any of the
Eight Analog Inputs Multiplexed Through
an 8:1 analog Switch
Can be Configured to Operate as a 4-wire,
5-wire, or 8-wire Resistive Touch Screen
Controller (TSC) Interface
– Up to Three External DMA Event Inputs That
Can Also be Used as Interrupt Inputs
– Eight 32-Bit General-Purpose Timers
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DMTIMER1 is a 1-ms Timer Used for
Operating System (OS) Ticks
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DMTIMER4 - DMTIMER7 are Pinned Out
– Up to Three 32-Bit Enhanced Capture
Modules (eCAP)
– One Watchdog Timer
– SGX530 3D Graphics Engine
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Configurable as Three Capture Inputs or
Three Auxiliary PWM Outputs
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Tile-Based Architecture Delivering Up to
20 Million Polygons per second
– Up to Three Enhanced High-Resolution PWM
Modules (eHRPWM)
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Universal Scalable Shader Engine is a
Multi-Threaded Engine Incorporating
Pixel and Vertex Shader Functionality
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Dedicated 16-Bit Time-Base Counter with
Time and Frequency Controls
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Advanced Shader Feature Set in Excess
of Microsoft VS3.0, PS3.0 and OGL2.0
Industry Standard API Support of
Direct3D Mobile, OGL-ES 1.1 and 2.0,
OpenVG 1.0, and OpenMax
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Configurable as Six Single-Ended, Six
Dual-Edge Symmetric, or Three Dual-
Edge Asymmetric Outputs
– Up to Three 32-Bit Enhanced Quadrature
Encoder Pulse (eQEP) Modules
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Fine-Grained Task Switching, Load
Balancing and Power Management
Advanced Geometry DMA Driven
Operation for Minimum CPU Interaction
Programmable High-Quality Image Anti-
Aliasing
Fully Virtualized Memory Addressing for
OS Operation in a Unified Memory
Architecture
• Device Identification
– Contains Electrical fuse Farm (FuseFarm) of
Which Some Bits are Factory Programmable
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Production ID
Device Part Number (Unique JTAG ID)
Device Revision (readable by Host ARM)
• Debug Interface Support
– JTAG and cJTAG for ARM (Cortex-A8 and
PRCM), PRU-ICSS Debug
– Supports Device Boundary Scan
– Supports IEEE 1500
• DMA
– LCD Controller
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Up to 24-Bits Data Output; 8-Bits per
Pixel (RGB)
Resolution Up to 2048x2048 (With
Maximum 126-MHz Pixel Clock)
Integrated LCD Interface Display Driver
(LIDD) Controller
Integrated Raster Controller
Integrated DMA Engine to Pull Data from
the External Frame Buffer without
– On-Chip Enhanced DMA Controller (EDMA)
has Three Third-Party Transfer Controllers
(TPTC) and One Third-Party Channel
Controller (TPCC), Which Supports Up to 64
Programmable Logical Channels and Eight
QDMA Channels. EDMA is Used for:
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Transfers to and from On-Chip Memories
Burdening the Processor via Interrupts or
Copyright © 2011–2013, Texas Instruments Incorporated
Device Summary
3
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