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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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5.11.1.2 McSPI—Master Mode
Table 5-83. McSPI Timing Conditions—Master Mode
LOW LOAD
MIN
HIGH LOAD
MIN
TIMING CONDITION PARAMETER
UNIT
MAX
MAX
Input Conditions
tr
Input signal rise time
Input signal fall time
8
8
8
ns
ns
tf
8
Output Condition
Cload
Output load capacitance
5
25
pF
Table 5-84. Timing Requirements for McSPI Input Timings—Master Mode
(see Figure 5-90)
OPP100
LOW LOAD HIGH LOAD
OPP50
NO.
LOW LOAD
HIGH LOAD
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, SPI_D[x]
4
5
tsu(SOMI-SPICLKH) (SOMI) valid before
2.29
3.02
2.29
3.02
ns
ns
SPI_CLK active edge(1)
Hold time, SPI_D[x]
th(SPICLKH-SOMI) (SOMI) valid after
SPI_CLK active edge(1)
4.7
4.7
4.7
4.7
(1) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Table 5-85. Switching Characteristics for McSPI Output Timings—Master Mode
(see Figure 5-91)
OPP100
OPP50
UNI
T
NO.
PARAMETER
LOW LOAD
MIN
HIGH LOAD
MIN
LOW LOAD
MIN
HIGH LOAD
MIN MAX
MAX
MAX
MAX
1
2
tc(SPICLK)
Cycle time, SPI_CLK
20.8
20.8
41.6
41.6
ns
Typical Pulse duration,
SPI_CLK low
tw(SPICLKL)
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1) ns
0.5P(1) ns
Typical Pulse duration,
SPI_CLK high
tw(SPICLKH)
3
tr(SPICLK)
tf(SPICLK)
Rising time, SPI_CLK
Falling time, SPI_CLK
3.82
3.44
3.82
3.44
3.82
3.44
3.82 ns
3.44 ns
Delay time, SPI_CLK active
edge to SPI_D[x] (SIMO)
transition(2)
6
7
td(SPICLK-SIMO)
-3.57
3.57
3.57
-4.62
4.62
4.62
-3.57
3.57
3.57
-4.62
4.62 ns
4.62 ns
Delay time, SPI_CS active
edge to SPI_D[x] (SIMO)
transition(2)
td(CS-SIMO)
Mode 1
A - 4.2(4)
B - 4.2(5)
B - 4.2(5)
A - 4.2(4)
A - 2.54(4)
B - 2.54(5)
B - 2.54(5)
A - 2.54(4)
A - 4.2(4)
B - 4.2(5)
B - 4.2(5)
A - 4.2(4)
A - 2.54(4)
B - 2.54(5)
B - 2.54(5)
A - 2.54(4)
ns
ns
ns
ns
Delay time,
SPI_CS active to
SPI_CLK first
and 3(3)
8
9
td(CS-SPICLK)
Mode 0
and 2(3)
edge
Mode 1
Delay time,
SPI_CLK last
edge to SPI_CS
and 3(3)
td(SPICLK-CS)
Mode 0
and 2(3)
inactive
(1) P = SPI_CLK period.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
(3) The polarity of SPIx_CLK and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable:
–
–
SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).
SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).
(4) Case P = 20.8 ns, A = (TCS+1)*TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
216 Peripheral Information and Timings
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