AM3359, AM3358, AM3357
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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
4.1.4 Digital Phase-Locked Loop Power Supply Requirements
The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor
of the AM335x device. The AM335x device integrates 5 different DPLLs—Core DPLL, Per DPLL, Display
DPLL, DDR DPLL, MPU DPLL.
Figure 4-7 illustrates the power supply connectivity implemented in the AM335x device. Table 4-1 provides
the power supply requirements for the DPLL.
MPU
PLL
PER
PLL
VDDS_PLL_MPU
VDDA1P8V_USB0
CORE
PLL
DDR
PLL
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
LCD
PLL
Figure 4-7. DPLL Power Supply Connectivity
Table 4-1. DPLL Power Supply Requirements
SUPPLY NAME
DESCRIPTION
MIN NOM MAX UNITS
VDDA1P8V_USB0
Supply voltage range for USBPHY and PER DPLL, Analog, 1.8V
Max. peak-to-peak supply noise
1.71 1.8
1.71 1.8
1.71 1.8
1.71 1.8
1.89
V
50 mV (p-p)
VDDS_PLL_MPU
Supply voltage range for DPLL MPU, Analog
Max. peak-to-peak supply noise
1.89
V
50 mV (p-p)
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
Supply voltage range for DPLL CORE and LCD, Analog
Max. peak-to-peak supply noise
1.89
V
50 mV (p-p)
Supply voltage range for DPLL DDR, Analog
Max. peak-to-peak supply noise
1.89
V
50 mV (p-p)
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Power and Clocking
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