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ADS62P49IRGCT 参数 Datasheet PDF下载

ADS62P49IRGCT图片预览
型号: ADS62P49IRGCT
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道14位/ 12位, 250 / 210 - MSPS ADC,具有DDR LVDS和并行CMOS输出 [Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs]
分类和应用: 双倍数据速率
文件页数/大小: 76 页 / 2133 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635AAPRIL 2009REVISED JUNE 2009  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
76  
0
0
<OFFSET PEDESTAL – Common/CH B>  
D5-D0  
<OFFSET PEDESTAL – Common/CH B>  
When the offset correction is enabled, the final converged value (after the offset is corrected) will  
be the ideal ADC mid-code value (=8192 for P49/48, = 2048 for P29/28). A pedestal can be  
added to the final converged value by programming these bits. So, the final converged value will  
be = ideal mid-code + PEDESTAL. See "Offset Correction" in application section.  
Applies to channel B (only with independent control).  
011111 PEDESTAL = 31 LSB  
011110 PEDESTAL = 30 LSB  
011101 PEDESTAL = 29 LSB  
….  
000000 PEDESTAL = 0  
….  
111111 PEDESTAL = –1 LSB  
111110 PEDESTAL = –2 LSB  
….  
100000 PEDESTAL = –32 LSB  
Copyright © 2009, Texas Instruments Incorporated  
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Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
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