ADS131M04-Q1
ZHCSOL7A –MARCH 2022 –REVISED AUGUST 2022
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9.4.2 Layout Example
图 9-6 shows an example layout of the ADS131M04-Q1 requiring a minimum of two PCB layers. In general,
analog signals and planes are partitioned to the left and digital signals and planes to the right.
+3.3 V
Via to corresponding
voltage plane or pour
+3.3 V
+3.3 V
Via to ground plane
or pour
Place CAP and power supply
decoupling capacitors close to pins
Channel 0
1: AVDD
2: AGND
3: AIN0P
4: AIN0N
5: AIN1N
6: AIN1P
7: AIN2P
8: AIN2N
9: AIN3N
10: AIN3P
20: DVDD
19: DGND
18: CAP
Channel 1
Channel 2
Channel 3
17: CLKIN
16: DIN
Device
15: DOUT
14: SCLK
13: DRDY
12: CS
11: SYNC/RST
Terminate long digital
input lines with resistors to
prevent reflection
Differential RC-filter
per channel
图9-6. Layout Example
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