ADS131M04-Q1
ZHCSOL7A –MARCH 2022 –REVISED AUGUST 2022
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8.6.4 CLOCK Register (Address = 3h) [reset = 0F0Eh]
The CLOCK register is shown in 图8-29 and described in 表8-17.
Return to the Summary Table.
图8-29. CLOCK Register
15
7
14
6
13
12
11
10
CH2_EN
R/W-1b
2
9
8
RESERVED
R-0000b
CH3_EN
R/W-1b
3
CH1_EN
R/W-1b
1
CH0_EN
R/W-1b
0
5
4
RESERVED
R/W-00b
TBM
OSR[2:0]
R/W-011b
PWR[1:0]
R/W-10b
R/W-0b
表8-17. CLOCK Register Field Descriptions
Bit
Field
Type
Reset
Description
15:12
RESERVED
R
0000b
Reserved
Always reads 0000b
11
CH3_EN
R/W
R/W
R/W
R/W
1b
1b
1b
1b
Channel 3 ADC enable
0b = Disabled
1b = Enabled (default)
10
9
CH2_EN
CH1_EN
CH0_EN
Channel 2 ADC enable
0b = Disabled
1b = Enabled (default)
Channel 1 ADC enable
0b = Disabled
1b = Enabled (default)
8
Channel 0 ADC enable
0b = Disabled
1b = Enabled (default)
7:6
5
RESERVED
TBM
R/W
R/W
00b
0b
Reserved
Always write 00b
Modulator oversampling ratio 64 selection (turbo mode)
0b = OSR set by bits 4:2 (that is, OSR[2:0])
1b = OSR of 64 is selected
4:2
OSR[2:0]
R/W
011b
Modulator oversampling ratio selection
000b = 128
001b = 256
010b = 512
011b = 1024 (default)
100b = 2048
101b = 4096
110b = 8192
111b = 16384
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