ADS131B04-Q1
ZHCSMK3B –NOVEMBER 2020 –REVISED NOVEMBER 2021
www.ti.com.cn
6.8 Timing Diagrams
tw(CLH)
tw(CLL)
CLKIN
DRDY
tw(DRL)
tw(DRH)
CS
SCLK
DIN
tw(SCL)
td(SCCS)
td(CSSC)
tc(SC)
tw(CSH)
tw(SCH)
tsu(DI)
th(DI)
tp(CSDO)
MSB
tp(SCDO)
tw(CSDOZ)
LSB
MSB - 1
LSB + 1
DOUT
SPI settings are CPOL = 0 and CPHA = 1. CS transitions must take place when SCLK is low.
图6-1. SPI Timing Diagram
CLKIN
tsu(SY)
tw(SYL)
tw(RSL)
SYNC/RESET
图6-2. SYNC/RESET Timing Requirements
90%
Supplies
tPOR
DRDY
图6-3. Power-On-Reset Timing
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: ADS131B04-Q1
TI [ TEXAS INSTRUMENTS ]
