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SBAS499A –JULY 2012–REVISED AUGUST 2012
LOFF: Lead-Off Control Register
Address = 04h
BIT 7
BIT 6
BIT 5
BIT 4
0
BIT 3
BIT 2
BIT 1
BIT 0
COMP_TH2
COMP_TH1
COMP_TH0
ILEAD_OFF1
ILEAD_OFF0
FLEAD_OFF1
FLEAD_OFF0
This register configures the lead-off detection operation.
Bits[7:5]
COMP_TH[2:0]: Lead-off comparator threshold
These bits determine the lead-off comparator threshold level setting. See the Lead-Off Detection subsection of the EEG-
Specific Functions section for a detailed description.
Comparator positive side
000 = 95% (default)
001 = 92.5%
010 = 90%
011 = 87.5%
100 = 85%
101 = 80%
110 = 75%
111 = 70%
Comparator negative side
000 = 5% (default)
001 = 7.5%
010 = 10%
011 = 12.5%
100 = 15%
101 = 20%
110 = 25%
111 = 30%
Bit 4
Must always be set to '0'
Bits[3:2]
ILEAD_OFF[1:0]: Lead-off current magnitude
These bits determine the magnitude of current for the current lead-off mode.
00 = 6 nA (default)
01 = 24 nA
10 = 6 µA
11 = 24 µA
Bits[1:0]
FLEAD_OFF[1:0]: Lead-off frequency
These bits determine the frequency of lead-off detect for each channel.
00 = DC lead-off detection (default)
01 = AC lead-off detection at 7.8 Hz (SYS_CLK / 218
)
10 = AC lead-off detection at 31.2 Hz (SYS_CLK / 216
11 = AC lead-off detection at fDR / 4
)
Copyright © 2012, Texas Instruments Incorporated
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