ADS1274
ADS1278
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SBAS367F –JUNE 2007–REVISED FEBRUARY 2011
POWER SUPPLIES
MODULATOR OUTPUT
The ADS1274/78 has three power supplies: AVDD,
DVDD, and IOVDD. AVDD is the analog supply that
powers the modulator, DVDD is the digital supply that
powers the digital core, and IOVDD is the digital I/O
power supply. The IOVDD and DVDD power supplies
can be tied together if desired (+1.8V). To achieve
rated performance, it is critical that the power
supplies are bypassed with 0.1μF and 10μF
capacitors placed as close as possible to the supply
pins. A single 10μF ceramic capacitor may be
substituted in place of the two capacitors.
The ADS1274/78 incorporates a 6th-order, single-bit,
chopper-stabilized modulator followed by
a
multi-stage digital filter that yields the conversion
results. The data stream output of the modulator is
available directly, bypassing the internal digital filter.
The digital filter is disabled, reducing the DVDD
current, as shown in Table 16. In this mode, an
external digital filter implemented in an ASIC, FPGA,
or similar device is required. To invoke the modulator
output, tie FORMAT[2:0], as shown in Figure 85.
DOUT[4:1]/[8:1] then becomes the modulator data
stream outputs for each channel and SCLK becomes
the modulator clock output. The DRDY/FSYNC pin
becomes an unused output and can be ignored. The
normal operation of the Frame-Sync and SPI
interfaces is disabled, and the functionality of SCLK
changes from an input to an output, as shown in
Figure 85.
Figure 84 shows the start-up sequence of the
ADS1274/78. At power-on, bring up the DVDD supply
first, followed by IOVDD and then AVDD. Check the
power-supply sequence for proper order, including
the ramp rate of each supply. DVDD and IOVDD may
be sequenced at the same time (for example, if the
supplies are tied together). Each supply has an
internal reset circuit whose outputs are summed
together to generate a global power-on reset. After
the supplies have exceeded the reset thresholds, 218
fCLK cycles are counted before the converter initiates
the conversion process. Following the CLK cycles,
the data for 129 conversions are suppressed by the
ADS1274/78 to allow output of fully-settled data. In
SPI protocol, DRDY is held high during this interval.
In frame-sync protocol, DOUT is forced to zero. The
power supplies should be applied before any analog
or digital pin is driven. For consistent performance,
assert SYNC after device power-on when data first
appear.
Table 16. Modulator Output Clock Frequencies
MODULATOR
CLOCK
OUTPUT
(SCLK)
ADS1274 ADS1278
MODE
[1:0]
DVDD
(mA)
DVDD
(mA)
CLKDIV
00
01
1
1
1
0
1
0
fCLK/4
fCLK/4
fCLK/8
fCLK/4
fCLK/40
fCLK/8
4.5
4.0
2.5
2.5
1.0
0.5
8
7
4
4
1
1
10
11
Modulator Data Channel 1
Modulator Data Channel 2
DOUT1
DOUT2
DVDD
IOVDD
AVDD
1V nom(1)
1V nom(1)
IOVDD
3V nom(1)
DIN
FORMAT0
Internal Reset
CLK
Modulator Data Channel 4/8(1)
Modulator Clock Output
FORMAT1 DOUT4/8(1)
FORMAT2
SCLK
218
129 (max)
tDATA
fCLK
(1) The ADS1274 has four channels; the ADS1278 has eight
channels.
DRDY
(SPI Protocol)
DOUT
(Frame-Sync Protocol)
Figure 85. Modulator Output
Valid Data
(1) The power-supply reset thresholds are approximate.
Figure 84. Start-Up Sequence
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