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ADS1278 参数 Datasheet PDF下载

ADS1278图片预览
型号: ADS1278
PDF下载: 下载PDF文件 查看货源
内容描述: 四/八通道,同步采样, 24位模拟至数字转换器 [Quad/Octal, Simultaneous Sampling, 24-Bit Analog-to-Digital Converters]
分类和应用: 转换器
文件页数/大小: 51 页 / 1452 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ADS1274  
ADS1278  
SBAS367F JUNE 2007REVISED FEBRUARY 2011  
www.ti.com  
tCSHD  
CLK  
tSCSU  
tSYN  
SYNC  
DRDY  
tNDR  
Figure 73. Synchronization Timing (SPI Protocol)  
Table 11. SPI Protocol  
SYMBOL  
tCSHD  
tSCSU  
tSYN  
DESCRIPTION  
MIN  
10  
5
TYP  
MAX  
UNITS  
CLK to SYNC hold time  
SYNC to CLK setup time  
Synchronize pulse width  
Time for new data to be ready  
ns  
ns  
1
CLK periods  
Conversions (1/fDATA)  
tNDR  
129  
tCSHD  
CLK  
tSCSU  
tSYN  
SYNC  
FSYNC  
DOUT  
tNDR  
Valid Data  
Figure 74. Synchronization Timing (Frame-Sync Protocol)  
Table 12. Frame-Sync Protocol  
SYMBOL  
tCSHD  
tSCSU  
tSYN  
DESCRIPTION  
MIN  
10  
5
TYP  
MAX  
UNITS  
CLK to SYNC hold time  
SYNC to CLK setup time  
Synchronize pulse width  
Time for new data to be ready(1)  
ns  
ns  
1
CLK periods  
Conversions (1/fDATA)  
tNDR  
127  
128  
(1) If SYNC is asynchronous to the FSYNC clock, then tNDR varies from 127 to 128 conversions, starting from the rising edge of SYNC. If  
SYNC is made synchronous to the FSYNC clock, then tNDR is stable.  
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© 20072011, Texas Instruments Incorporated  
Product Folder Link(s): ADS1274 ADS1278  
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