ADC0801, ADC0802
ADC0803, ADC0804, ADC0805
SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013
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SAMPLE PROGRAM FOR Figure 60 ADC0801–MC6820 PIA INTERFACE
The following schematic and sample subroutine (DATA IN) may be used to interface (up to) 8 ADC0801’s directly
to the MC6800 CPU. This scheme can easily be extended to allow the interface of more converters. In this
configuration the converters are (arbitrarily) located at HEX address 5000 in the MC6800 memory space. To
save components, the clock signal is derived from just one RC pair on the first converter. This output drives the
other A/Ds.
All the converters are started simultaneously with a STORE instruction at HEX address 5000. Note that any other
HEX address of the form 5XXX will be decoded by the circuit, pulling all the CS inputs low. This can easily be
avoided by using a more definitive address decoding scheme. All the interrupts are ORed together to insure that
all A/Ds have completed their conversion before the microprocessor is interrupted.
The subroutine, DATA IN, may be called from anywhere in the user’s program. Once called, this routine
initializes the CPU, starts all the converters simultaneously and waits for the interrupt signal. Upon receiving the
interrupt, it reads the converters (from HEX addresses 5000 through 5007) and stores the data successively at
(arbitrarily chosen) HEX addresses 0200 to 0207, before returning to the user’s pro- gram. All CPU registers then
recover the original data they had before servicing DATA IN.
Auto-Zeroed Differential Transducer Amplifier and A/D Converter
The differential inputs of the ADC0801 series eliminate the need to perform a differential to single ended
conversion for a differential transducer. Thus, one op amp can be eliminated since the differential to single ended
conversion is provided by the differential input of the ADC0801 series. In general, a transducer preamp is
required to take advantage of the full A/D converter input dynamic range.
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