ADC0801, ADC0802
ADC0803, ADC0804, ADC0805
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SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013
Figure 57. INS8048 Interface
SAMPLE PROGRAM FOR Figure 57 INS8048 INTERFACE
Interfacing the Z-80
The Z-80 control bus is slightly different from that of the 8080. General RD and WR strobes are provided and
separate memory request, MREQ, and I/O request, IORQ, signals are used which have to be combined with the
generalized strobes to provide the equivalent 8080 signals. An advantage of operating the A/D in I/O space with
the Z-80 is that the CPU will automatically insert one wait state (the RD and WR strobes are extended one clock
period) to allow more time for the I/O devices to respond. Logic to map the A/D in I/O space is shown in
Figure 58.
Figure 58. Mapping the A/D as an I/O Device for Use with the Z-80 CPU
Additional I/O advantages exist as software DMA routines are available and use can be made of the output data
transfer which exists on the upper 8 address lines (A8 to A15) during I/O input instructions. For example, MUX
channel selection for the A/D can be accomplished with this operating mode.
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