THCV231-Q_THCV236-Q_Rev.2.60_E
Table 49. 2-wire serial slave AC Timing (Sub-Link Master device)
Symbol
fSCL
tHD;STA
tLOW
Parameter
Min
-
0.6
1.3
0.6
-
20
500
100
-
Typ
-
-
-
Max
400
-
-
-
-
-
-
Unit
kHz
us
us
us
us
ns
ns
ns
SCL clock frequency
Hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
tHIGH
-
Data hold time: output
Data hold time: input
Data setup time: output
Data setup time: input
9×tOSC
tHD;DAT
-
-
-
-
tSU;DAT
-
tr
tf
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
(pull-up resistor:2.5kΩ,bus capacitance:400pF)
Setup time for STOP condition
Bus free time between a STOP and START condition
Pulse width of spikes which must be suppressed by the input
filter
300(*1)
ns
-
-
300
ns
tSU;STO
tBUF
0.6
1.3
-
-
-
-
ns
us
tSP
-
-
-
50
-
ns
tPDS
Required wait time from PDN1 high to START condition
2
ms
*1 Please adjust Pull-up resistor and bus capacitance to meet the spec value.
Table 50. 2-wire serial master AC Timing (Sub-Link Slave device)
Symbol
Parameter
Min
Typ
Max
Unit
tOSC
Cycle of internal oscillator clock
10.417
12.5
15.625
ns
(SCL_W_H × 8 – 3)
tHD;STA
tLOW
Hold time (repeated) START condition
LOW period of the SCL clock
-
-
-
-
us
us
× tOSC
((SCL_W_L + 1) × 8 + 8)
× tOSC
((SCL_W_H + 1) × 8 +
tHIGH
HIGH period of the SCL clock
-
8)
-
us
× tOSC
Data hold time: output
Data hold time: input
Data setup time: output
Data setup time: input
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
(pull-up resistor:2.5kΩ, bus
capacitance:400pF)
-
20
31×tOSC
100
-
9×tOSC
-
-
-
-
us
ns
ns
ns
ns
tHD;DAT
-
-
-
-
tSU;DAT
tr
300(*1)
tf
-
-
300
ns
tSU;STO
tBUF
Setup time for STOP condition
Bus free time between a STOP and START
condition
-
386×tOSC
-
-
-
ns
us
4.7
*1 Please adjust Pull-up resistor and bus capacitance to meet the spec value.
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