THCV231-Q_THCV236-Q_Rev.2.60_E
Table 21. Sub-Link slave register Read Procedure
Step
Description
R/W
Address
1
Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).
Set Device ID of Sub-Link Master device.
W
0x02 bit7
2
3
W
W
0x20
0x22
(Value corresponding to AIN1 and AIN0 setting. e.g. [AIN1,AIN0]=[0,0] → 7’h0B)
Set the byte number read from Sub-Link Slave(Max 16byte).
(Byte number = register value + 1)
4
5
Set the start address of Sub-Link Slave register to read.
W
W
0x24
Write 1 to RD_START_8B. (Start read access to Sub-Link Slave register)
2-wire serial slave of Sub-Link Master perform clock stretching until Sub-Link Slave
register access is completed. When read access is completed, SCL is released and
read data is stored in Sub-Link Master register (Address 0x10-0x1F).
When read access is completed, read data is stored in Sub-Link Master register
(Address 0x10-0x1F) and 2WIRE_ACS_END_INT register value become 1 and
interrupt occurs (INT=H → L).
0x26 (*1)
6
-
-
-
-
(*2)
6
(*3)
7
8
If read access was normally ended, read value should be “0x1”.
HOST MPU read data stored in Sub-Link Master register.
R
R
0x02
0x10-0x1F
*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)
*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)
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