THCV231-Q_THCV236-Q_Rev.2.60_E
Data Width and Frequency Range Select Function
The THCV231-Q and THCV236-Q support a variety of data width and frequency range. Frequency range is
different depending on the mode setting SSCG enable and disable setting. Refer to Table 16 for details.
Table 16. Main-Link Operation Mode Select
Freq.Range
[MHz]
Main-Link
CML
Mode Setting
Data Width
SSCG
SSCG
Comment
Disable
Enable (*1)
Bit Rate
MAINMODE
HFSEL
COL1
COL0
min
max
min
max
Data
Sync
0
0
0
0
*
1
0
0
0
*
-
-
100
133.3
-
-
26.6
33.3
-
-
-
-
2
2
-
Forbidden
0
0
1
0
1
0
15
20
-
100
133.3
-
x40
x30
-
12
12
-
Forbidden
(*2)
50
70
12
15
20
-
70
160
30
40
75
50
70
26.6
26.6
33.3
-
70
160
60
75
100
-
0
1
0
1
x20
12
2
-
-
-
-
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
x50
x40
x30
-
14
14
14
-
-
-
-
Forbidden
Forbidden
-
-
-
-
(*2)
50
70
50
70
50
70
70
160
70
160
70
160
50
70
50
70
50
70
70
160
70
160
70
160
1
1
1
1
1
0
1
1
1
0
1
x20
x15
x15
14
10
-
(*2)
-
(*2) (*3)
1(*3)
8
2
(*3)
*1 Note that register setting is required depending on the mode setting and used frequency range. See Table 7.
*2 Register setting is required. See Table 17.
*3 While Register MAINMODE setting = 1, however, behavior of this exceptional setting is V-by-One® HS Mode whose meaning is MAINMODE = 0.
Table 17. Register setting (HFSEL=1 and Frequency range is from 50MHz to 70MHz)
Register Address(HEX)
Register Value(HEX)
THCV231-Q THCV236-Q
0x01
Step
Description
Sub-Link
Sub-Link
Master side
Slave side
1
2
3
4
0x70
0x76
0x78
0x7C
0xF0
0xF6
0xF8
0xFC
Set 1 to PLL_SET_EN
Set PLL_SET0
Set PLL_SET1
0x02
0x01
0x20
0x24
Set PLL_SET2
Data Mapping
Table 18. Data Mapping
MAINMODE
HFSEL
COL1
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
0
1
1
1
1
COL0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D0/RAW4
D1/RAW5
D2/RAW6
D3/RAW7
D4/RAW8
D5/RAW9
D6/RAW10
D7/RAW11
D8/RAW0
D9/RAW1
D10/RAW2
D11/RAW3
DE*2 (HSYNC*3)
VSYNC
D0/RAW4
D1/RAW5
D2/RAW6
D3/RAW7
D4/RAW8
D5/RAW9
D6/RAW10
D7/RAW11
D8/RAW0
D9/RAW1
D10/RAW2
D11/RAW3
DE*2 (HSYNC*3)
VSYNC
D0/RAW4/YC0
D1/RAW5/YC1
D2/RAW6/YC2
D3/RAW7/YC3
D4/RAW8/YC4
D5/RAW9/YC5
D6/RAW10/YC6
D7/RAW11/YC7
D8/RAW0
D9/RAW1
D10/RAW2
D11/RAW3
DE*2 (HSYNC*3)
VSYNC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D0/RAW4
D1/RAW5
D2/RAW6
D3/RAW7
D4/RAW8
D5/RAW9
D6/RAW10
D7/RAW11
D8/RAW0
D9/RAW1
D10/RAW2
D11/RAW3
HSYNC*1
VSYNC*1
D0/YC0
D1/YC1
D2/YC2
D3/YC3
D4/YC4
D5/YC5
D6/YC6
D7/YC7
-
D0/RAW0/YC0
D1/RAW1/YC1
D2/RAW2/YC2
D3/RAW3/YC3
D4/RAW4/YC4
D5/RAW5/YC5
D6/RAW6/YC6
D7/RAW7/YC7
-
D9
D9
D9
D9
-
-
-
-
-
-
D10
D11
HSYNC
VSYNC
D10
D11
HSYNC*1
VSYNC*1
D10
D11
HSYNC*1
VSYNC*1
D10
D11
HSYNC*1
VSYNC*1
HSYNC*1
VSYNC*1
DE*2 (HSYNC*3)
VSYNC*1
*1 Any signal as well as sync signal can be transmitted when MAINMODE=1.
*2 V-by-One®HS mode operation requires Data Enable (DE) signal rule. Please refer to the related section.
*3 HSYNC signal can be assigned to Data Enable input when V-by-One® HS mode requirements are met.
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