THCV231-Q_THCV236-Q_Rev.2.60_E
Table 14. Sub-Link Field BET Operation Setting
THCV231-Q/THCV236-Q
Common Setting
THCV231-Q
Setting
THCV236-Q
Setting
Condition
Sub-Link
Output
Latch
Select
BET
BET_SEL
PDN
GPIO3
GPIO4
PDN1
MSSEL
LATEN
Field BET
Operation
(THCV231-Q→THCV236-Q)
Field BET
Operation
(THCV236-Q→THCV231-Q)
1
0
1
-
1
0
(*3)
Latched
Result
1
(*1)
1
(*2)
1
1
1
(*3)
-
*1 THCV231-Q: Register setting (0x53 bit1), THCV236-Q: Pin setting. Note that BET pin should be 0 at power on sequence.
*2 Register setting (0x53 bit0, Default 0)
*3 Forbidden 0 setting
Table 15. Sub-Link Slave device Sub-Link Field BET Result
BETOUT
Output
Bit Error Occurred
No Error
L
H
Figure 5. Main-Link Field BET Configuration
THCV231-Q
THCV236-Q
Test Pattern
Generator
Test Pattern
Checker
OSC
RF/BETOUT
Test Point
for
Sub-Link
Field BET
BET=1 BET_SEL=1
(Register) (Register)
BET=1 BET_SEL=1
LATEN/SD3/AIN1/GPIO0 =1
(Pin)
(Register)
Figure 6. Sub-Link Field BET Configuration
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