欢迎访问ic37.com |
会员登录 免费注册
发布采购

78Q8430-100IGT/F 参数 Datasheet PDF下载

78Q8430-100IGT/F图片预览
型号: 78Q8430-100IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100以太网MAC和PHY [10/100 Ethernet MAC and PHY]
分类和应用: 电信集成电路编码器以太网局域网(LAN)标准
文件页数/大小: 88 页 / 1209 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
 浏览型号78Q8430-100IGT/F的Datasheet PDF文件第38页浏览型号78Q8430-100IGT/F的Datasheet PDF文件第39页浏览型号78Q8430-100IGT/F的Datasheet PDF文件第40页浏览型号78Q8430-100IGT/F的Datasheet PDF文件第41页浏览型号78Q8430-100IGT/F的Datasheet PDF文件第43页浏览型号78Q8430-100IGT/F的Datasheet PDF文件第44页浏览型号78Q8430-100IGT/F的Datasheet PDF文件第45页浏览型号78Q8430-100IGT/F的Datasheet PDF文件第46页  
78Q8430 Data Sheet  
DS_8430_001  
6.7.4.2 Source Address Filtering  
Source address filtering can be used to drop frames with a specific address while passing all others.  
Table 30 contains the rules on processing source address.  
Table 30: Process Source Address Rules  
Rule# PrevHit PH-Mask Data D-Mask Next Offset Action Interrupt Comment  
0x2F  
0x2E  
0x30  
0x30  
0x70  
0x70  
0x01  
0x00  
0x01  
0x00  
DROP 0x00  
MD 0x05  
NOP  
NOP  
0
0
MC drop  
pass other  
6.7.4.3 Length/Type Field, MAC Control Frames and IP Header Checksum  
Table 31 contains the rules on processing length/type, MAC control frames and start IP header checksum  
check.  
Table 31: Process Length/Type, MAC Control Frames and Start IP Header Checksum Rules  
Rule# PrevHit PH-Mask Data  
D-Mask Next Offset Action Interrupt Comment  
0x2D 0x2B  
0x2C 0x00  
0x7F  
0x00  
0x7F  
0x7F  
0x7C  
0x7F  
0x7F  
0x7C  
0x7F  
0x7F  
0x7E  
0x7F  
0x7F  
0x7F  
0x7F  
0x7F  
0x7F  
0x7F  
0x7F  
0x00  
0x00  
0x81  
0x00  
0x88  
0x08  
0x00  
0x00  
0x00  
0x40  
0x00  
0x00  
0x00  
0x01  
0x00  
0x00  
0x00  
0x3D  
0x00  
0xFF  
0x00  
0xFF  
0x00  
0xFF  
0xFF  
0x00  
0x00  
0x00  
0xF0  
0x00  
0xFF  
0x00  
0xFF  
0x00  
0x00  
0x00  
0xFF  
0x00  
MD  
DONE 0x00  
MD 0x00  
DONE 0x00  
0x02  
VLAN  
NOP  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x2B  
0x2A  
0x29  
0x28  
0x27  
0x26  
0x25  
0x24  
0x23  
0x22  
0x21  
0x20  
0x1F  
0x1E  
0x2E  
0x2B  
0x2F  
0x29  
0x29  
0x2F  
0x26  
0x25  
0x24  
0x28  
0x28  
0x22  
0x22  
0x20  
TDLTH  
TDLTL  
TDLTH  
MCTL  
TDLTL  
TDLTH  
TDLTL  
IPCK  
MD  
MD  
0x00  
0x00  
DONE 0x00  
MD  
MD  
MD  
MD  
MD  
0x00  
0x00  
0x00  
0x3F  
0x00  
TXA  
NOP  
DONE 0x00  
MD 0x00  
DONE 0x00  
NOP  
NOP  
MCTL pause  
MCTL other  
NOP  
MD  
MX  
0x00  
0x00  
TDPH  
TDPL  
PAUSE  
NOP  
0x1D 0x1E  
0x1C 0x1D  
DONE 0x00  
DONE 0x00  
0x1B  
0x1D  
MCTL pause  
with bad SRC  
6.7.4.4 Wake on LAN  
The packet classification engine can use the WAKE action to signal the host to come out of power down  
mode. This is used to implement the Wake-On-LAN feature.  
The Power Management Control and Status Register (PMCSR) is used to control the hardware response  
to a WAKE action. If the PS field of the PMCSR is zero then all WAKE actions are ignored. The  
WAKE action is only honored if the part is currently in a power down mode as determined by the  
PS field. If the PME_ENB bit in the PMCSR is set then a valid WAKE action will trigger the assertion of  
the PMEB primary output. If the PME_ENB bit is clear then a valid WAKE action will only result in the  
normal HIR WAKE interrupt.  
When the host is notified of a valid WAKE event, either by the assertion of the PMEB primary output or  
assertion of INTB via the WAKE HIR interrupt, the rule that triggered the event can be read from the  
Wake Up Status Register (WUSR). A valid WAKE event will also start the Host Not Responding (HNR)  
timer. When the host is notified of a WAKE event, it must clear the event by setting the PME bit in the  
42  
Rev. 1.2  
 
 
 复制成功!