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78Q8430-100IGT/F 参数 Datasheet PDF下载

78Q8430-100IGT/F图片预览
型号: 78Q8430-100IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100以太网MAC和PHY [10/100 Ethernet MAC and PHY]
分类和应用: 电信集成电路编码器以太网局域网(LAN)标准
文件页数/大小: 88 页 / 1209 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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78Q8430 Data Sheet  
DS_8430_001  
6.7.2 Configuring the CAM  
The CAM rules are accessed indirectly one at a time via the CAM Address Register (CAR). The contents  
of the rule whose number is indicated by the CAR are available for read and write via the Rule Match  
Register (RMR) and the Rule Control Register (RCR). The RMR contains a template that the CAM  
reference word must match in order to trigger the rule, and the RCR contains the control word that is  
passed to the control logic when the rule is triggered.  
6.7.2.1 Rule Match Register  
The RMR contains four fields that control when a rule is triggered: Previous Hit Match and Previous Hit  
Mask, Data Match and Data Mask. The mask fields are used to determine which bits in their respective  
match field are required to make a match and which bits are ignored. A mask bit value of one means that  
the corresponding match bit must be exactly equal to the same bit in the CAM reference word to trigger  
the rule. Inversely, a mask bit value of zero means that the corresponding bit in the CAM reference word  
is ignored. A special case is that all previous hit mask bits are zero. In this case, the rule is deactivated  
and can never be triggered.  
6.7.2.2 Rule Control Register  
The RCR contains four fields that control the actions taken by the control logic when the rule is triggered:  
Byte Offset, Interrupt, Action and Match Control fields.  
RCR Byte Offset  
The Byte Offset field is generally used to skip over bytes in the frame that are not relevant to the current  
classification. When the Byte Offset is non-zero then the classification will skip the number of bytes  
indicated. The exception is when the TOC action is used, in which case, the value of the Byte Offset field  
is used to initialize the control logic counter and no offset is applied.  
An offset value of 0x3F will skip just the right number of bytes to jump over the current IPv4 header.  
RCR Interrupt  
When the Interrupt bit in the RCR for a given rule is set, then the triggering of the rule will cause an HIR  
classification interrupt.  
Control Logic Action  
The value of the control logic Action field in the RCR determines the action that will be taken by the  
control logic when the rule is triggered.  
Table 26: Control Logic Actions  
Hex  
Value Value  
Binary  
Name  
Action Taken  
0x0  
0x2  
0x4  
0x6  
0x7  
0x8  
0xA  
0xC  
00000b  
00010b  
00100b  
00110b  
00111b  
01000b  
01010b  
01100b  
NOP  
No action taken.  
PAUSE Start the local pause timer.  
WAKE  
IPCK  
TIPO  
TDX  
Send a wake-up signal to the host and start the HNR timer.  
Start the IP header checksum check and the IP header counter.  
Transfer IP header counter to offset.  
‘X’ is assigned the value of the frame data.  
TAX  
‘X’ is assigned the value of the current rule number.  
TAXH  
The high-order nibble of ‘X’ is assigned the value of the low-order nibble  
of the current rule number.  
0xD  
01110b  
TAXL  
The low-order nibble of ‘X’ is assigned the value of the low-order nibble  
of the current rule number.  
0x10  
0x12  
10000b  
10010b  
TXA  
The classification result is assigned the value of ‘X’.  
TLXA  
The low-order nibble of the classification result is assigned the value of  
the low-order nibble of ‘X’.  
38  
Rev. 1.2