78Q8430 Data Sheet
DS_8430_001
5 Host Interface Timing Specification
5.1 Host Interface
CS
WR/OE
MEMWAIT
ADDR
DATA
TSL
TWT
THWT THCS
TSU
THOWT
THO
TL
TH
Figure 8: Host Interface Timing Diagram
Requirement
Name
Description
Min
Max
TSU
CS and ADDR setup time
CS and ADDR must be stable on or
before the falling edge of WR/OE.
0 ns
–
TSL
Output settling time
The maximum amount of time that it will
take the MEMWAIT, or DATA when there
is no MEMWAIT, outputs to become
stable after the falling edge of WR/OE.
–
13.7 ns
TWT
Maximum wait time
Wait hold time
The maximum amount of time that the
MEMWAIT output will held asserted.
–
17 ck
–
THWT
The minimum amount of time that the
WR/OE input must be held past the
de-assertion of MEMWAIT.
10 ns
THCS
THO
CS hold time
The CS input must be stable low for the
entire duration of the WR/OE low cycle.
0 ns
–
–
ADDR and DATA hold time The ADDR and DATA inputs must be
stable for no less than this amount of time
after the falling edge of WR.
2.5 ck
TL
WR/OE min low pulse
The minimum amount of time that the
WR/OE inputs must be held low.
2 ck
2 ck
–
–
TH
WR/OE min high pulse
The minimum amount of time that the
WR/OE inputs must be held high.
Note: On read cycles when MEMWAIT is asserted the DATA outputs will be valid before the
de-assertion of MEMWAIT.
22
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
