DS_8430_001
78Q8430 Data Sheet
6 Functional Description
6.1 Internal Block Diagrams
6.1.1 Internal Digital Block
Figure 12 presents an overview of the functional layers of the 78Q8430. On the left side are the signals,
which connect to the GBI bus. On the upper and middle right, the blocks that implement the MAC side of
the MII are shown. These blocks are connected to the embedded PHY. On the lower right, connections
to the EEPROM are shown.
Memory
Manager
MII
Register
Controller
Network
Wake-up
BUSCLK
RESETB
INTB
EMI
System
Flow
Control
MAC Half
Duplex
PMEB
4 Queue
Write Logic
EMI
Address
& Data
ADDR
DATA
Queue
Memory
MAC MII
Transmit
1 Queue
Read Logic
Queue
Read/Write
Logic
BUSMODE
CLKMODE
WAITMODE
BOOTSZ[1:0]
ENDIAN[1:0]
CSB
Snoop
Controller
MAC
MII
Receive
Bus
Control
CTL
Controller
Packet
Classify
RMON
WRB/OEB
MEMWAIT
TCLK
TMS
TDI
JTAG
IEEE
1149.1
Boundary
Scan
CAM
PROM_CS
PROM_CLK
PROM_DO
PROM_DI
EEPROM/
ROM
Control
TX/RX
Packet Status
Register
QUE Status
Register
DMA Status
Register
MAC Status
Register
TDO
TRSTB
Figure 12: Internal Digital Block Diagram
6.1.2 Internal PHY
Figure 13 shows the functional blocks of the internal 78Q8430 PHY. The signals shown on the left side
are the internal MII signals to the MAC. These signals are multiplexed with their respective external pins
for use with an external PHY device. The 78Q8430 is not a two-port device. Only one PHY interface can
be operational.
Rev. 1.2
25
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
