78Q8430 Data Sheet
DS_8430_001
NRZ/NRZI
MLT3 Encoder
4B/5B Encoder
Scrambler,
Parallel to Serial
TXOP
Pulse Shaper
and Filter
UTP
Driver
100M
10M
TXON
TX_CLK
MII
Transmit
Logic
TXD[3:0]
TX_EN
LINK
TXA
Tx Clock
Generator
TX_ER
LED0
LED1
RXA
LED
Control
Logic
Parallel to Serial
Manchester
Encoder
COLI
Interrupt
INTR
Logic
100BT
10BT
MII
Activity
Carrier Sense,
Collosion Detect
CRS
COL
FDX
Auto
Negotiation
RX_CLK
RXD[3:0]
RX_DV
RX_ER
MII
Receive
Logic
Manchester
Decoder,
Serial to Parallel
RXIP
RXIN
10M
UTP
Receiver
Clock
Recovery
Adaptive Equalizer,
Baseline Wander,
MLT3 Decoder,
NRZI/NRZ
100M
Serial to Parallel
Descrambler,
5B/4B Decoder
MII
Registers
MDC
MDIO
Clock
Reference
XTLP/CLKIN
XTLN
VCC
GND
Figure 13: Internal PHY Block Diagram
On the right side are the signals, which connect to the status LEDs and a 1:1 isolation transformer before
connecting to an RJ-45 connector, or equivalent media components.
6.2 Data Queuing
Ethernet frame data in the 78Q8430 is managed in queuing structures called QUEs. The host bus
address space allocated for QUEs has enough space for eight, while the 78Q8430 circuit only
implements five. QUEs are identified numerically, QUE0 through QUE7, based on the registers in the
QUE register space that are used to access them. QUE1, QUE6 and QUE7 are unimplemented and
reserved for future use.
A QUE allocates main buffer memory as needed and stores discrete frames as they are written into the
QUE. The QUE then reads back frames in the same order that they were written and frees the main
buffer memory. A QUE can contain a maximum of 125 frames at any one time. If a QUE is unable to
allocate main buffer memory when writing a frame, the frame will be partially added to the QUE as a
truncated frame. If a QUE is unable to allocate main buffer memory to start a frame, the entire frame is
dropped.
The QUEs are divided into two categories: receive QUEs, that store received frame data and transmit
QUEs, that store transmit frame data. Frames are written to a receive QUE by the MAC and read out by
the host. Frames are written to a transmit QUE by the host and read out by the MAC. QUE0 and QUE1
are receive QUEs (only QUE0 is implemented), and QUE2 through QUE7 are transmit QUEs (QUE2
through QUE5 are implemented). Writing to the Transmit Data Register (TDR) for a receive QUE or
reading from the Read Data Register (RDR) for a transmit QUE is not supported and the result is
undefined in this specification.
The transmit QUEs are further divided into standard QUEs, as described above, and static QUEs. Static
QUEs differ from the standard QUEs in that they can only contain a single frame, and that frame must be
252 bytes or less in total size. Unlike standard QUEs, static QUEs do not remove a frame when it is read
from the QUE. Once a frame is written to a static QUE, it can be read out any number of times and the
static QUE will always read out the same one frame. If a second frame is written to a static QUE then it
will replace the first as the one frame contained in the QUE.
26
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
