78Q8430 Data Sheet
DS_8430_001
3.2.8 Mode Pins
Table 9: Chip Mode Pin Descriptions
Type Description
Signal
Pin Number
BUSMODE
CLKMODE
WAITMODE
83
85
84
I
I
I
BUSMODE, CLKMODE, WAITMODE Configuration
0,0,0 = Sync bus, ext. system clock, memwait act low
0,0,1 = Sync bus, ext. system clock, memwait act high
0,1,0 = Reserved
0,1,1 = Reserved
1,0,0 = Async bus, ext. system clock, memwait act low
1,0,1 = Async bus, ext. system clock, memwait act high
1,1,0 = Async bus, int. system clock, memwait act low
1,1,1 = Async bus, int. system clock, memwait act high
ENDIAN0
ENDIAN1
79
80
I
I
Data Bus Endian Select
0,0 = Big endian (MSB at high bit positions)
0,1 = Bytes are little endian inside 16-bit words
1,0 = Word endian (MSW at low bit positions)
1,1 = Little endian (MSB at low bit positions)
BOOTSZ1
BOOTSZ0
100
1
I
I
GBI Bus Size
BOOTSZ[1:0]: is strapped to indicate the GBI bus size:
00 = Bus is 32 bits wide
01 = Bus is 16 bits wide. Only DATA[15:0] are used.
10 = Bus is 8 bits wide. Only DATA[7:0] are used.
11 = Reserved
Notes:
1. The internal PHY should never be powered down when the internal system clock is selected by
the CLKMODE pin (CLKMODE=1)
2. There is no external visibility for the system clock when the internal clock mode is selected. The
GBI interface must therefore always be used in asynchronous bus mode.
3.2.9 JTAG Pins
Table 10: JTAG Pin Descriptions
Signal
Type Description
Pin Number
5
I
Test Reset (active low)
TRST
System provided reset for JTAG logic.
TCLK
TMS
6
3
I
Test Clock
System provided clock for JTAG logic.
IU
Test Mode Select
Enables JTAG boundary scan using serial in/serial out ports.
Sampled on rising edge of TCLK.
TDI
4
IU
O
Test Data In
Serial input port for clocking in test data to be shifted to the
output at the end of the boundary scan chain (TDO).
TDO
81
Test Data Out
Serial output port for clocking out test data shifted from the
input at the beginning of the boundary scan chain (TDI).
16
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
