78Q2123/78Q2133 MicroPHY™
10/100BASE-TX Transceiver
REGISTER DESCRIPTION
The 78Q2123/78Q2133 implement 13 16-bit registers, which are accessible via the MDIO and MDC pins. The
supported registers are shown below in the following table. Attempts to read unsupported registers will be
ignored and the MDIO pin will not be enabled as an output, as per the IEEE 802.3 specification. All of the
registers except those that are unique to the 78Q2123/78Q2133 will respond to the broadcast PHYAD value of
‘00000’. The registers specific to the 78Q2123/78Q2133 occupy address space MR16-24.
ADDRESS
SYMBOL
MR0
NAME
DEFAULT (HEX)
(3100)
(7849)
000E
0
1
Control
MR1
Status
2
MR2
PHY Identifier 1
3
MR3
PHY Identifier 2
7237
4
MR4
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
Not Implemented
(01E1)
0000
5
MR5
6
MR6
0000
7
MR7
0000
8-14
15
16
17
18
19
20-22
23
24
MR8-14
MR15
MR16
MR17
MR18
MR19
MR20-22
MR23
MR24
Reserved
0000
Not Implemented
0000
Vendor Specific
(0140)
0000
Interrupt Control/Status Register
Diagnostic Register
Transceiver Control
Reserved
0000
4XXX
0000
LED Configuration Register
MDI/MDIX Control Register
0010
(00C0)
Legend:
TYPE DESCRIPTION
TYPE DESCRIPTION
R
Readable by management.
W
Writeable by management.
WC
Writeable by management. Self
Clearing.
RC
Readable by management.
Cleared upon a read operation.
0/1
Default value upon power up or
reset
Page: 11 of 42
© 2009 Teridian Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
