78Q2123/78Q2133 MicroPHY™
10/100BASE-TX Transceiver
MR0: Control Register
BIT
0.15
SYMBOL TYPE DEFAULT DESCRIPTION
RESET
R/WC
0
Reset: Setting this bit to ‘1’ resets the device and sets all registers to
their default states. This bit is self-clearing.
0.14
LOOPBK
R/W
0
Loopback: When this bit is set to ‘1’, input data at TXD[3:0] is output
at RXD[3:0]. No transmission of data on the network medium occurs
and receive data on the network medium is ignored. By default, the
loopback signal path encompasses most of the digital functional
blocks. This bit allows for diagnostic testing.
0.13 SPEEDSL R/W
1
1
Speed Selection: This bit determines the speed of operation of the
78Q2123/78Q2133. Setting this bit to ‘1’ indicates 100Base-TX
operation and a ‘0’ indicates 10Base-T mode. This bit will default to a
‘1’ upon reset. When auto-negotiation is enabled, this bit will not be
writable and will have no effect on the 78Q2123/78Q2133. If auto-
negotiation is not enabled, this bit may be written to force manual
configuration.
0.12
ANEGEN
R/W
Auto-Negotiation Enable: The auto-negotiation process is enabled by
setting this bit to ‘1’. This bit will default to ‘1’. If this bit is cleared to
‘0’, manual speed and duplex mode selection is accomplished through
bits 0.13 (SPEEDSL) and 0.8 (DUPLEX) of the Control Register.
0.11
0.10
PWRDN
ISO
R/W
R/W
0
0
Power-Down: The device may be placed in a low power consumption
state by setting this bit to ‘1’. While in the power-down state, the
device will still respond to management transactions.
Isolate: When set to ‘1’, the device will present a high-impedance on
its MII output pins. This allows for multiple PHY’s to be attached to
the same MII interface. When the device is isolated, it still responds to
management transactions.
0.9
0.8
RANEG
R/WC
R/W
0
1
Restart Auto-Negotiation: Normally, the Auto-Negotiation process is
started at power up. The process can be restarted by setting this bit
to ‘1’. This bit is self-clearing.
DUPLEX
Duplex Mode: This bit determines whether the device supports full-
duplex or half-duplex. A ‘1’ indicates full-duplex operation and a ‘0’
indicates half-duplex. This bit will default to ‘1’ upon reset. When
auto-negotiation is enabled, this bit will not be writable and will have
no effect on the 78Q2123/78Q2133. If auto-negotiation is not
enabled, this bit may be written to force manual configuration.
0.7
COLT
RSVD
R/W
R
0
0
Collision Test: When this bit is set to ‘1’, the device will assert the
COL signal in response to the assertion of the TX_EN signal.
Collision test is disabled if the PCSBP bit, MR16.1, is high. Collision
test can be activated regardless of the duplex mode of operation.
0.6:0
Reserved
Page: 12 of 42
© 2009 Teridian Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
