78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
PIN DESCRIPTION (continued)
CONTROL PINS
NAME
PIN
TYPE DESCRIPTION
FIFO Phase-Initialization Control:
When asserted, the transmit FIFO pointers are reset to the respective
“centered” states. Also resets the FIERR interrupt bit. De-assertion edge of
FRST will resume FIFO operation.
•
Low: FRST assertion.
Float/High: Normal
59
CIT
FRST
•
Because the internal VCO clock and off-chip transmit clocks may not be stable
during transmit power-up, it is recommended to always reset the FIFOs after
powering up the IC or the transmitter.
Not valid during Plesiochronous Serial Mode.
Redundant Channel Selection:
Enables the redundant Transmit Monitor Output at pins CMI2P/N.
14
15
CID
CIT
RCSL
LPBK
•
Low: Normal operation (CMIP/N active only)
•
High: Transmit Monitor Mode (CMIP/N and CMI2P/N active)
Analog Loopback Selection:
•
Low: Normal operation
•
Float: Remote Loopback Enable: Recovered receive data and clock
are looped back to the transmitter for retransmission.
•
High: Local Loopback Enable: The serial transmit data is looped back
and used as the input to the receiver.
Clock Mode Selection:
Selects the method of inputting transmit data into the chip. See
TRANSMITTER OPERATION section for more information.
In PARALLEL mode (SDI_PAR high):
•
Low: Parallel transmit clock is input to the 78P2351.
•
Float: Parallel transmit clock is input to the 78P2351. Loop-timing
mode enabled.
13
CIT
CKMODE
•
High: Parallel transmit clock is output from the 78P2351
In SERIAL mode (SDI_PAR low):
•
•
•
Low: Reference clock is synchronous to transmit clock and data. Data
is clocked in with SICKP/N and passed through a FIFO
Float: Reference clock is synchronous to transmit data. Clock is
recovered with a CDR and data is passed through a FIFO
High: Reference clock is plesiochronous to transmit data. Clock is
recovered with a CDR and the FIFO is bypassed
Page: 20 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
