78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
PIN DESCRIPTION (continued)
REFERENCE AND STATUS PINS
NAME
PIN
TYPE DESCRIPTION
Reference Clock Input:
A required reference clock input used for clock/data recovery and frequency
synthesizer. Options include
83
82
PI/
CI
CKREFP
CKREFN
• 139.264 MHz (E4) or 155.52 MHz (STM1) differential LVPECL clock
input at CKREFP/N
• 17.408 MHz (E4), 19.44 MHz (STM1), or 77.78 MHz (STM1) single-
ended CMOS clock input at CKREFP. Tie CKREFN to ground when
unused.
Receive Loss of Signal (active-high):
See Receiver Loss of Signal description for conditions.
61
60
OD
OD
LOS
LOL
Receive Loss of Lock (active-high):
This condition is met when the recovered clock frequency differs from the
reference clock frequency by more than +/- 100ppm.
Transmitter Fault Interrupt Flag (active low):
When a transmitter error event occurs (as defined in the Interrupt Control
Register Description), the INTTXB pin will change state to indicate an
interrupt. The interrupt is cleared by a read to the STAT Register, an issue
of a FRST FIFO reset pulse (if the FIERR signal caused the interrupt), or
when the TXLOL register bit transitions from high to low.
67
OD
INTTXB
Note: The default interrupt condition is a loss of lock in the transmitter CDR.
Receiver Fault Interrupt Flag (active-low):
Reserved for future use.
52
64
OD
A
INTRXB
PORB
Power-On Reset (active-low):
See Power-On Reset description on use of this pin.
Page: 19 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
