78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
PIN DESCRIPTION (continued)
RECEIVER PINS
NAME
PIN
TYPE DESCRIPTION
Receive Data (Parallel Mode) Output:
41
40
37
36
PO0D
PO1D
PO2D
PO3D
Recovered receive data de-serialized into four-bit CMOS parallel (nibble)
outputs. The MSB (PO3D) is received first. Active, but undefined during
reset.
CO
CO
Note: During Loss of Signal conditions, data outputs are held low.
Receive (Parallel Mode) Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output generated by
dividing down the recovered receive clock. By default, receive data is
clocked out on the falling edge. Active during reset.
33
POCK
Note: During Loss of Signal conditions, the clock will remain on the last
divided down phase selection of the Rx DLL and output a steady clock.
Receive (Serial Mode) Data Output:
20
21
SODP
SODN
Recovered receive serial NRZ data at LVPECL levels. Active, but undefined
PO
PO
during reset.
Note: During Loss of Signal conditions, data outputs are held at logic 0.
Receive (Serial Mode) Clock Output:
Recovered receive serial clock. By default, recovered serial NRZ data is
18
19
SOCKP
SOCKN
clocked out the falling edge of SOCKP. Active during reset.
Note: During Loss of Signal conditions, the clock will remain on the last
phase selection of the Rx DLL and output a steady clock.
Receiver (CMI or NRZ) Input:
90
91
A/
PI
RXP
RXN
The input is either transformer-coupled to coaxial cable for CMI data or AC-
coupled at LVPECL levels to an optical transceiver module for NRZ data.
Page: 18 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
