DS_6612_001
78M6612 Data Sheet
Name
Location
Rst Wk
Dir
Description
RTC_DEC_SEC
RTC_INC_SEC
201C[1]
201C[0]
0
0
0
0
W
RTC time correction bits. Only one bit may be pulsed at a
time. When pulsed, causes the RTC time value to be
incremented (or decremented) by an additional second
the next time the RTC_SEC register is clocked. The pulse
width may be any value. If an additional correction is
desired, the MPU must wait 2 seconds before pulsing one
of the bits again. Each write to one of these bits must be
preceded by a write to 201F (WE).
RTM_E
2002[3]
0
0
R/W Real Time Monitor enable. When ‘0’, the RTM output is
low. This bit enables the 2 wire version of RTM
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
2060
2061
2062
2063
0
0
0
0
0
0
0
0
R/W Four RTM probes. Before each CE code pass, the values
of these registers are serially output on the RTM pin. The
RTM registers are ignored when RTM_E=0.
SECURE
SFRB2[6]
0
–
R/W Enables security provisions that prevent external reading
of Flash memory and CE program RAM. This bit is reset
on chip reset and may only be set. Attempts to write zero
are ignored.
SLEEP
20A9[6]
0
0
W
Takes the 78M6612 to sleep mode. Ignored if system
power is present. The part will wake when the autowake
timer times out or when system power returns.
SUM_CYCLES[5:0]
TMUX[4:0]
2001[5:0]
20AA[4:0]
0
2
0
–
R/W The number of pre-summer outputs summed in the final
summer.
R/W Selects one of 32 signals for TMUXOUT.
[4:0]
0x00
0x02
0x04
0x06
0x08
0x0A
Selected Signal [4:0]
Selected Signal
0x01 Reserved
0x03 Reserved
DGND (analog)
Reserved
Reserved
0x05 Reserved
0x07 Not used
0x09 Reserved
VBIAS (analog)
Reserved
Reserved
0x0
B -
Reserved
0x13
0x14
RTM (Real time 0x15 WDTR_E, comparator
output from CE)
1 Output AND V1LT3)
0x16
–
0x17
Not used
0x18 RXD, from optical in-
terface, after optional
inversion
0x19
0x1B
0x1D
0x1F
MUX_SYNC
CK_MPU
0x1
A
CK_10M
Reserved
CE_BUSY
0x1
C
RTCLK_2P5
XFER_BUSY
0x1
E
VERSION[7:0]
2006[7:0]
–
–
R
The version index. This word may be read by firmware to
determine the silicon version.
VERSION[7:0]
0000 0110
VREF_CAL
VREF_DIS
2004[7]
2004[3]
0
0
0
1
R/W Brings VREF to VREF pad. This feature is disabled when
VREF_DIS=1.
R/W Disables the internal voltage reference.
Rev. 1.2
81
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
