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78M6612-IMR/F 参数 Datasheet PDF下载

78M6612-IMR/F图片预览
型号: 78M6612-IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 单相,双插座电源和电能计量IC [Single-Phase, Dual-Outlet Power and Energy Measurement IC]
分类和应用: 插座
文件页数/大小: 111 页 / 1528 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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78M6612 Data Sheet  
DS_6612_001  
Name  
Location  
Rst Wk  
Dir  
Description  
MUX_DIV[1:0]  
2002[7:6]  
0
0
R/W The number of states in the input multiplexer.  
00 – Illegal  
01 – 4 states 10 – 3 states 11 – 2 states  
OPT_FDC[1:0]  
2007[1:0]  
0
0
R/W Selects TX1 modulation duty cycle.  
OPT_FDC  
Function  
00  
01  
10  
11  
50% Low  
25% Low  
12.5% Low  
6.25% Low  
RX1DIS  
2008[5]  
0
0
R/W RX1 can be configured as an analog input to the UART1  
comparator or as a digital input/output, DIO1.  
0—RX1, 1—DIO1.  
RX1INV  
2008[4]  
0
0
R/W Inverts result from RX1 comparator when 1. Affects only  
the UART1 input. Has no effect when RX1 is used as a  
DIO input.  
TX1E[1,0]  
2007[7,6]  
00  
00  
R/W Configures the TX1 output pin.  
00—TX1, 01—DIO2, 10—WPULSE, 11—VARPULSE  
TX1INV  
2008[0]  
2008[1]  
0
0
0
0
R/W Invert TX1 when 1. This inversion occurs before  
modulation.  
TX1MOD  
R/W Enables modulation of TX1. When TX1MOD is set, TX1 is  
modulated when it would otherwise have been zero. The  
modulation is applied after any inversion caused by  
TX1INV.  
PLL_OK  
2003[6]  
0
0
R
Indicates that system power is present and the clock  
generation PLL is settled.  
PLS_MAXWIDTH  
[7:0]  
2080[7:0]  
FF  
FF  
R/W Determines the maximum width of the pulse (low going  
pulse).  
Maximum pulse width is (2*PLS_MAXWIDTH + 1)*TI.  
Where TI is PLS_INTERVAL. If PLS_INTERVAL=0, TI is  
the sample time (397µs). If 255, disable MAXWIDTH.  
PLS_INTERVAL  
[7:0]  
2081[7:0]  
2004[6]  
0
0
0
0
R/W If the FIFO is used, PLS_INTERVAL must be set to 81. If  
PLS_INTERVAL = 0, the FIFO is not used and pulses are  
output as soon as the CE issues them.  
PLS_INV  
R/W Inverts the polarity of WPULSE and VARPULSE.  
Normally, these pulses are active low. When inverted,  
they become active high.  
PREBOOT  
SFRB2[7]  
2001[7:6]  
0
0
R
Indicates that preboot sequence is active.  
The duration of the pre-summer, in samples.  
00-42, 01-50, 10-84, 11-100.  
PRE_SAMPS[1:0]  
R/W  
RTC_SEC[5:0]  
RTC_MIN[5:0]  
RTC_HR[4:0]  
RTC_DAY[2:0]  
RTC_DATE[4:0]  
RTC_MO[3:0]  
RTC_YR[7:0]  
2015  
2016  
2017  
2018  
2019  
201A  
201B  
R/W The RTC interface. These are the ‘year’, ‘month’, ‘day’,  
R/W ‘hour’, ‘minute’ and ‘second’ parameters of the RTC. The  
R/W RTC is set by writing to these registers. Year 00 and all  
R/W others divisible by 4 are defined as leap years.  
R/W  
R/W  
R/W  
SEC 00 to 59  
MIN 00 to 59  
HR  
00 to 23 (00=Midnight)  
DAY 01 to 07 (01=Sunday)  
DATE 01 to 31  
MO 01 to 12  
YR  
00 to 99  
Each write to one of these registers must be preceded by  
a write to 201F (WE).  
80  
Rev. 1.2  
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