DS_6612_001
78M6612 Data Sheet
Name
Location
Rst Wk
Dir
Description
INTBITS
SFRF8[6:0]
–
–
R/W Interrupt inputs. The MPU may read these bits to see the
input to external interrupts INT0, INT1, up to INT6. These
bits do not have any memory and are primarily intended
for debug use.
LCD_BLKMAP19[3:0]
LCD_BLKMAP18[3:0]
205A[7:4]
205A[3:0]
0
0
–
–
R/W Identifies which segments connected to SEG18 and
SEG19 should blink. 1 means ‘blink.’ Most significant bit
corresponds to COM3. Least significant, to COM0.
LCD_CLK[1:0]
2021[1:0]
R/W Sets the LCD clock frequency (for COM/SEG pins, not
frame rate).
Note: fw = 32768 Hz
00: fw/29, 01: fw/28, 10: fw/27, 11: fw/26
LCD_E
2021[5]
0
0
–
–
R/W Enables the LCD display. When disabled, VLC2, VLC1,
and VLC0 are ground as are the COM and SEG outputs.
LCD_MODE[2:0]
2021[4:2]
R/W The LCD bias mode.
000: 4 states, ⅓ bias
001: 3 states, ⅓ bias
010: 2 states, ½ bias
011: 3 states, ½ bias
100: static display
LCD_NUM[4:0]
2020[4:0]
0
–
R/W Number of dual-purpose LCD/DIO pins to be configured
as LCD. This will be a number between 0 and 18. The
first dual-purpose pin to be allocated as LCD is
SEG41/DIO21 (SEG40/DIO20 on the 64 LQFP package).
Thus if LCD_NUM=2, SEG41 and SEG 40 will be
configured as LCD. The remaining SEG39 to SEG24 will
be configured as DIO19 to DIO4.
DIO1 and DIO2 (plus DIO3 on the QFN-68 package) are
always available, if not used for UART1.
See tables in Application Section.
LCD_ONLY
20A9[5]
0
0
W
Takes the 78M6612 to LCD mode. Ignored if system
power is present. The part will awaken when autowake
timer times out or when system power returns.
LCD_SEG0[3:0]
…
LCD_SEG19[3:0]
2030[3:0]
…
2043[3:0]
0
…
0
–
…
–
R/W LCD Segment Data. Each word contains information for
from 1 to 4 time divisions of each segment. In each
word, bit 0 corresponds to COM0, on up to bit 3 for COM3.
These bits are preserved in LCD and SLEEP
modes, even if their pin is not configured as
SEG. In this case, they can be useful as
general-purpose non-volatile storage.
LCD_SEG24[3:0]
…
LCD_SEG38[3:0]
2048[3:0]
…
2056[3:0]
0
…
0
–
…
–
R/W
LCD_Y
2021[6]
0
0
R/W LCD Blink Frequency (ignored if blink is disabled or if
segment is off).
0: 1 Hz (500 ms ON, 500 ms OFF)
1: 0.5 Hz (1s ON, 1s OFF)
MPU_DIV[2:0]
2004[2:0]
0
0
R/W The MPU clock divider (from 4.9152 MHz). These bits
may be programmed by the MPU without risk of losing
control.
000-4.9152 MHz, 001-4.9152 MHz /21, …, 111-4.9152
MHz /27
MPU_DIV remains unchanged when the part enters
BROWNOUT mode.
MUX_ALT
2005[2]
0
0
R/W The MPU asserts this bit when it wishes the MUX to
perform ADC conversions on an alternate set of inputs.
Rev. 1.2
79
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
