73S8010C
Low Cost Smart Card Interface
DATA SHEET
TYPICAL APPLICATION SCHEMATIC
AUX2UC_to/from_uC
AUX1UC_to.from_uC
I/OUC_to/from_uC
See NOTE 5
See note 7
See NOTE 3
SAD0
SAD1
SAD2
External_clock_from uC
- OR -
C2
VDD
22pF
Y1
C3
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R3
SAD0
SAD1
SAD2
GND
GND
VPC
NC
AUX2UC
AUX1UC
I/OUC
Rext2
C4
C5
3
22pF
CRYSTAL
VPC
4
XTALOUT
XTALIN
100nF
10uF
5
See NOTE 4
6
INT
GND
7
VDD
See note 2
See NOTE 1
8
NC
VDD
9
NC
SDA
C6
100nF
10
11
12
13
14
PRES
I/O
SCL
VDDF_ADJ
VCC
AUX2
AUX1
GND
R1
RST
Rext1
R4
2K
R5
2K
CLK
See note 6
73S8010R
SO28
INT_interrupt_to_uC
SDA_to/from_uC
SCK_from_uC
VDD
R2
NOTES:
1) VDD = 2.7V to 5.5V DC.
2) VPC = 4.75V(EMV, ISO) to 5.5V DC
ISO7816=1uF, EMV=3.3uF
Low ESR (<100mohms) C1
should be placed near the SC
connecter contact
Card detection
switch is
20K
C1
normally closed
3) Required if external clock from uP is used.
4) Required if crystal is used.
CLK track should be routed
far from RST, I/O, C4 and
C8.
Y1, C2 and C3 must be removed if external clock is used.
5) Optional. Can be left open.
6) R1 and R3 are external resistors that adjust the VDD
Smart Card Connector
fault voltage. Can be left open.
7) Hardware to define address of device
Figure 10: 73S8010R – Typical Application Schematic
Page: 15 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
