73S8010R
Low Cost Smart Card Interface
DATA SHEET
I/O CIRCUITRY AND TIMING
The states of the I/O, AUX1, and AUX2 pins are low after power-on-reset and they are high when the activation
sequencer enables the I/O reception state. See Activation Sequence timing section for more details on when the
I/O reception is enabled. The states of the I/OUC, AUX1UC, and AUX2UC are high after power on reset. When
the control I/O enable bit 7 of control register is set, the first I/O line on which a falling edge is detected becomes
the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected then
both I/O lines return to their neutral state. The delay between these signals is shown in Figure 9.
IO
IOUC
tIO_HL
tIOUC_HL
tIOUC_LH
tIO_LH
Delay from I/O to I/OUC:
Delay from I/OUC to I/O:
tIO_HL = 100ns
tIO_LH = 25ns
tIOUC_LH = 25ns
tIOuc_HL = 100ns
Figure 9 - I/O Timing Definition
Page: 14 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
