73S8010R
Low Cost Smart Card Interface
DATA SHEET
SYMBOL PARAMETER
Condition
MIN
Typ.
MAX
UNIT
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC.
ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC.
IOH =0
IOH = -40µA
IOH =0
0.9 VCC
0.75 VCC
0.9 VDD
VCC+v0.1
VCC + 0.1
VDD+0.1
VDD + 0.1
0.3
V
V
V
V
V
Output level, high (I/O,
VOH
AUX1, AUX2)
Output level, high (I/OUC,
AUX1UC, AUX2UC)
VOH
0.75 VDD
IOH = -40µA
VOL
VIH
Output level, low
I =1mA
OL
Input level, high (I/O, AUX1,
AUX2)
1.8
VCC +0.30
V
Input level, high (I/OUC,
AUX1UC, AUX2UC)
Input level, low
VIH
VIL
1.8
VDD +0.30
V
-0.3
0.8
0.1
0.3
10
V
V
V
µA
mA
IOL = 0
Output voltage when outside
VINACT
of session
I
OL = 1mA
ILEAK
IIL
Input leakage
Input current, low
VIH = VCC
VIL = 0
0.65
For output low,
shorted to VCC
ISHORTL
Short circuit output current
15
mA
mA
through 33 ohms
For output high,
shorted to ground
through 33 ohms
CL = 80pF, 10% to
90% For I/OUC,
AUX1UC, AUX2UC,
CL=50pF
ISHORTH
Short circuit output current
15
tR, tF
Output rise time, fall times
100
ns
tIR, tIF
RPU
Input rise, fall times
1
14
1
µs
kΩ
Output stable for
>200ns
Internal pull-up resistor
8
11
MHz
FDMAX
Maximum data rate
Delay, I/O to I/OUC,
I/OUC to I/O, AUX1 to
AUX1UC, AUX1UC to
AUX1, AUX2 to AUX2UC,
AUX2UC to AUX2
Falling edge from
master to slave
measured at 50%
point
TFDIO
60
100
200
ns
Delay, I/O to I/OUC,
I/OUC to I/O, AUX1 to
AUX1UC, AUX1UC to
AUX1, AUX2 to AUX2UC,
AUX2UC to AUX2
Rising edge from
master to slave
measured at 50%
point
TRDIO
25
90
10
ns
CIN
Input capacitance
pF
Page: 18 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
