73S8010R
Low Cost Smart Card Interface
DATA SHEET
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C-bus Read from Status Register:
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C-bus Read Command from the Status Register follows the format shown below. After the START condition, a
slave address is sent by the master. This address is seven bits long followed by an eighth bit which is an opcode
bit (R/W) – a ‘one’ indicates the master will read data from the status register. After the R/W bit, the ’zero’ ACK bit
is sent to the master by the device. The device now starts sending the 8-bit status register data to the control
register during the DATA bits. After the DATA bits, the ‘one’ ACK bit is sent to the device by the master. The
master should send the STOP condition after receiving the ACK bit.
SDA
MSB
SCL
1-7
LSB
8
9
MSB
1-8
LSB
9
START
condition
ADDRESS bits
R/W bit
ACK bit
DATA bits
ACK bit
STOP
condition
Figure 3 - I
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C Bus Read Protocol
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C-bus timing definition:
SDA
Tbuf
SCL
Thi
T lo w
T h d s ta
T sudat
Thddat
T s u s to
Figure 4 - I
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C Bus Timing Definitions
Symbol
Fsclk
Tlow
Thi
Thdsta
Tsudat
Thddat
Tsusto
Tbuf
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Parameter
Clock frequency
Clock low
Clock high
Hold time START condition
Data set up time
Data hold time
Set up time STOP condition
Bus free time between a STOP
and START condition
Min.
1.3
0.6
0.6
100
5
0.6
1.3
Typ.
Max.
400
Unit
kHz
µs
µs
µs
ns
ns
µs
µs
Rev 1.5
900
©
2005-2008 TERIDIAN Semiconductor Corporation
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
