73S8010R
Low Cost Smart Card Interface
DATA SHEET
ACTIVATION SEQUENCE
After Power on Reset, the signal INT is low until the VDD is stable. When VDD has been stable for approximately
10 ms and the signal INT is high, the system controller may read the status register to see if the card is present. If
all the status bits are satisfied, the system controller can initiate the activation sequence by writing a ‘1’ to
Start/Stop bit (bit 0) of control register.
The following steps show the activation sequence and the timing of the card control signals when the system
controller initiates the Start/Stop bit (bit 0) of the control register:
-
Voltage VCC to the card should be valid by the end of t1. If VCC is not valid for any reason, then the
session is aborted.
-
-
-
Turn I/O to reception mode at the end of t1.
CLK is applied to the card at the end of t2.
RST (to the card) is set high at the end of t3.
Start/Stop
VCC
IO
CLK
RST
t1
t2
t3
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator), I/O in reception mode
t2 =1.5µs, CLK starts
t3 = >42000 card clock cycles, RST set high
Figure 5 - Activation Sequence
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© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
