DS_8010C_024
73S8010C Data Sheet
13 Typical Application Schematic
See NOTE 5
AUX2UC_to/f rom_uC
AUX1UC_to.f rom_uC
IOUC_to/from_uC
VDD
SAD0
SAD1
SAD2
Note 2
See NOTE 3
R5
External_clock_f rom uC
Rext2
- OR -
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SAD0
SAD1
SAD2
GND
GND
VPC
NC
NC
NC
PRES
I/O
AU X2
AU X1
GND
AUX2UC
AUX1UC
I/OUC
XTALOUT
XTALIN
INT_
C4
C5
C2
100nF
10uF
L1 10uH
See note 7
22pF
Y1
C3
GND
VDD
SDA
SCL
See NOTE 1
C6
CRYSTAL
22pF
VDD_ADJ
VCC
100nF
PWRDN_from_uC
R4
See NOTE 4
RST
CLK
See NOTE 5
Rext1
R3 2K
73S8010C
SO28
R2 2K
See
note 6
INT_interrupt_to_uC
VDD
R1
SDA_f rom_uC
SCL_f rom_uC
20K
ISO7816=1uF, EMV=3.3uF
Low ESR (<1 00mohms) C1
NOTES:
1) VDD supply should be = 2.7V to 3.6V DC.
2) Hardwire to define address of device
3) Required if external clock from uP is used.
4) Required if crystal is used.
Y1, C2 and C3 must be removed if external clock is used.
5) Pin can not float. Must be driven or connected to GND
if power down function is not used.
should be placed near the SC
connecter contact
Card detection
switch is normally
closed.
C1
CLK track should be routed
far from RST, I/O, C4 and
C8.
6) Rext1 and Rext2 are external resistors to ground and
VDD to modify the VDD fault voltage. Can be left open
7) Keep L1 close to pin 5
Smart Card Connector
Figure 11: 73S8010C – Typical Application Schematic
Rev. 1.5
15
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
