DS_8009R_056
73S8009R Data Sheet
Choice of the VCC capacitor:
Depending on the application, the requirements in terms of both the VCC minimum voltage and the
transient currents that the interface must be able to provide to the card are different. An external
capacitor must be connected between the VCC pin and the card ground in order to guarantee stability of
the LDO regulator, and to handle the transient requirements. The type and value of this capacitor can be
optimized to meet the desired specification. Table 8 shows the recommended capacitors for each VPC
power supply configuration and applicable specification.
Table 8: Choice of VCC Pin Capacitor
Specification Requirements
Min VCC Voltage
System Requirements
Max Transient
Min VPC Power
Capacitor
Type
Capacitor
Value
allowed during
Specification
Current Charge Supply required
transient current
EMV 4.1
4.6 V
4.5 V
30 nAs
20 nAs
4.75 V
4.75 V
3.3 µF
1 µF
X5R/X7R
with
ESR<100 mΩ
ISO-7816-3 &
GSM11.11
3.5 Over-temperature Monitor
A built-in detector monitors die temperature. When an over-temperature condition occurs, a card
deactivation sequence is initiated, and an error or fault condition is reported to the system controller via
the OFF interrupt.
3.6 Activation and Deactivation Sequence
The host controller is fully responsible for the activation sequencing of the smart card signals CLK, RST,
I/O, AUX1 and AUX2. All of these signals are held low when the card is in the deactivated state. Upon
card activation (the fall of CMDVCC#/CMDVCC%, all the signals will remain low until RDY goes high. The
host should set the signals RSTIN, I/OUC, CLKIN, AUX1UC and AUX2UC low prior to activating the card
and allow RDY to go high before transitioning any of these signals. In order to initiate activation, the card
must be present and there can be no over-temperature fault and no VDD fault.
At t1 (500 µs), if RDY = 0 or overcurrent, circuit will de-activate (safety feature)
t1
CMDVCC3 or CMDVCC5
VCC
IOUC
IO
VCC valid
Ignored
IO = IOUC if RDY=1
RDY
Ignored
Ignored
RSTIN
RST
RST=RSTIN if RDY=1
CLKIN
CLK
CLK=CLKIN if RDY=1
IO, AUX1, AUX2, CLK, RST are held LOW until RDY = 1 and CMDVCCx = 0
Figure 5: Activation Sequence
Rev. 1.3
15
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
