DS_8009R_056
73S8009R Data Sheet
3 Applications Information
This section provides general usage information for the design and implementation of the 73S8009R.
3.1 Example 73S8009R Schematics
Figure 4 shows a typical application schematic for the implementation of the 73S8009R. Note that minor changes may occur to the reference
material from time to time and the reader is encouraged to contact Teridian for the latest information.
CS_from_uC
VDD
OFF_interrupt_to_uC
I/OUC_to/from_uC
See NOTE 1
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CS
TEST1
N/C
OFF
VDD
GND
PRES
I/O
AUX1
AUX2
VCC
RST
GND
CLK
N/C
N/C
PRES
VPC
C6
100nF
AUX1UC_to/from_uC
AUX2UC_to/from_uC
I/OUC
AUX1UC
AUX2UC
CMDVCC5
CMDVCC3
RSTIN
CLKIN
RDY
CMDVCC5_from_uC
CMDVCC3_from_uC
See NOTE 4
VDD
VPC
RSTIN_from_uC
CLKIN_from_uC
PWRDN
TEST2
See NOTE 2
C4
C5
RDY_status_to_uC
100nF
10uF
PWRDN_from_uC
73S80009R
SO28
See NOTE 3
VDD
R
2
20K
ISO7816=1µF, EMV=3.3µF
Card detection
switch is
normally closed
Low ESR (<100mohms) C1
should be placed near the SC
connecter contact
C1
NOTES:
1) VDD = 2.7V to 3.6V DC.
2) VPC = 4.75V to 6.0V DC (Class A-B-C Reader: 1.8V, 3V and 5V cards)
3) Must be tied to GND if not used
CLK track should be routed
far from RST, I/O, C4 and C8
4) Internal pull-up allows it to be left open if unused.
Smart Card Connector
Figure 4: Typical 73S8009R Application Schematic
Rev. 1.3
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TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
