欢迎访问ic37.com |
会员登录 免费注册
发布采购

73S8009R 参数 Datasheet PDF下载

73S8009R图片预览
型号: 73S8009R
PDF下载: 下载PDF文件 查看货源
内容描述: 低成本通用智能卡接口 [Low Cost Versatile Smart Card Interface]
分类和应用:
文件页数/大小: 23 页 / 337 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
 浏览型号73S8009R的Datasheet PDF文件第14页浏览型号73S8009R的Datasheet PDF文件第15页浏览型号73S8009R的Datasheet PDF文件第16页浏览型号73S8009R的Datasheet PDF文件第17页浏览型号73S8009R的Datasheet PDF文件第19页浏览型号73S8009R的Datasheet PDF文件第20页浏览型号73S8009R的Datasheet PDF文件第21页浏览型号73S8009R的Datasheet PDF文件第22页  
73S8009R Data Sheet  
DS_8009R_056  
3.9 Chip Select  
The CS pin is provided to allow multiple circuits to operate in parallel, driven from the same host control  
bus. When CS is high, the pins RSTIN, CMDVCC%, CMDVCC# and CLKIN control the chip as described.  
The pins IOUC, AUX1UC, and AUX2UC operate to transfer data to the smart card via IO, AUX1, and  
AUX2 when the smart card is activated. IO, AUX1, and AUX2 have 11 Kpull-up resistors while OFF  
and RDY have 20 Kpull-up resistors.  
When CS goes low, the states of the pins RSTIN, CMDVCC%, CMDVCC#, and CLKIN are latched and  
held internally. The pull-up for pins IOUC, AUX1UC, and AUX2UC become a very weak pull-up of  
approximately 3 microamperes. No transfer of data is possible between IOUC, AUX1UC, AUX2UC and  
the smart-card signals IO, AUX1, and AUX2. The signals OFF and RDY are set to high impedance and  
the internal 20 Kpull-up resistors are disconnected. PWRDN is not latched when CS is low.  
The operation of the fault sensing circuits and card sense inputs (in regards to de-activation) are not  
affected by CS.  
tDZ  
CS  
tSL  
OFF, I/OUC, AUX1UC,  
AUX2UC  
HI-Z STATE  
HI-Z STATE  
FUNCTIONAL  
CONTROL SIGNALS  
tID  
tIS  
tDI  
tSI  
Figure 9: CS Timing Definitions  
3.10 I/O Circuitry and Timing  
The states of the I/O, AUX1, and AUX2 pins are low after power-on-reset and they are high when the  
activation sequencer enables the I/O reception state. See Section 3.6 Activation and Deactivation  
Sequence for more details on when the I/O reception is enabled. The states of the I/OUC, AUX1UC, and  
AUX2UC are high after power on reset.  
Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling  
edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input  
I/O line rising edge is detected, both I/O lines return to their neutral state.  
Figure 10 shows the state diagram of how the I/O and I/OUC lines are managed to become input or  
output. The delay between the I/O signals is shown in Figure 11.  
18  
Rev. 1.3