DS_1217F_002
73S1217F Data Sheet
Pin Name
Description
INT3
INT2
SIO
48
49
47
I
I
Figure 35 General purpose interrupt input.
Figure 35 General purpose interrupt input.
IO
Figure 31 IO data signal for use with external Smart Card interface
circuit such as 73S73S8010x.
SCLK
PRES
45
53
O
I
Figure 32 Clock signal for use with external Smart Card interface
circuit.
Figure 44 Smart Card presence. Active high. Note: the pin has a very
weak pull down resistor. In noisy environments, an external
pull down may be desired to insure against a false card
event.
CLK
RST
IO
55
57
61
60
59
58
O
O
Figure 42 Smart card clock signal.
Figure 42 Smart card Reset signal.
IO
Figure 43 Smart card Data IO signal.
Figure 43 Auxiliary Smart Card IO signal (C4).
Figure 43 Auxiliary Smart Card IO signal (C8).
AUX1
AUX2
VCC
IO
IO
PSO
Smart Card VCC supply voltage output. A 0.47μF capacitor
is required and should be located at the smart card
connector. The capacitor should be a ceramic type with low
ESR.
GND
VPC
56
65
GND
PSI
Smart Card Ground.
Power supply source for main voltage converter circuit. A
10μF and a 0.1μF capacitor are required at the VPC input.
The 10μF capacitor should be a ceramic type with low ESR.
VBUS
VBAT
62
64
PSI
PSI
Alternate power source input from USB connector or hub.
Alternate power source input, typically from two series cells,
V > 4V.
VP
54
66
PSO
PSI
Intermediate output of main converter circuit. Requires an
external 4.7μF low ESR filter capacitor to GND.
LIN
Connection to 10μH inductor for internal step up converter.
Note: inductor must be rated for 400 mA maximum peak
current.
ON_OFF
63
I
Figure 46 Power control pin. Connected to normally open SPST switch
to ground. Closing switch for duration greater than de-
bounce period will turn 73S1217F on. If 73S1217F is on,
closing switch will flag the 73S1217F to go to the off state.
Firmware will control when the power is shut down.
Rev. 1.2
9
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
