DS_1217F_002
73S1217F Data Sheet
1.2 Hardware Overview
The 73S1217F single smart card controller integrates all primary functional blocks required to implement
a smart card reader with host serial and / or USB interface. Included on chip are an 8051-compatible
microprocessor (MPU) which executes up to one instruction per clock cycle (80515), a fully integrated IS0
7816 compliant smart card interface, expansion smart card interface, full speed USB 2.0 compatible
interface, serial interface, I2C interface, 6 x 5 keypad interface, RAM, FLASH memory, a real time clock
(RTC), and a variety of I/O pins.
Advanced power management features include a DC-DC converter and on-chip regulators that generate
all the necessary voltages for the circuit: Primarily a smart card supply VCC, (selectable to 1.8V, 3V or
5V) and a 3.3V digital voltage output (VDD, pin #68) that must be connected to the power supply inputs of
the digital core of the circuit, pins # 28 and 40 (these are not internally connected). Should external
circuitry require a 3.3V digital power supply, the VDD output is capable of supplying additional current.
The whole IC can be powered up either from a USB bus-power supply (VBUS +5V typical), or from a
typical set of battery cells VBAT. Automated switching between these supply inputs give the priority to
VBUS to save the battery life.
A functional block diagram of the 73S1217F is shown in Figure 1.
1.3 80515 MPU Core
1.3.1 80515 Overview
The 73S1217F includes an 80515 MPU (8-bit, 8051-compatible) that performs most instructions in one
clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution
of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most
of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (average)
improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Actual processor clocking speed can be adjusted to the total processing demand of the application
(cryptographic calculations, key management, memory management, and I/O management) using the
XRAM special function register MPUCKCtl.
Typical smart card, USB, serial, keyboard, I2C and RTC management functions are available for the
MPU as part of the Teridian standard library. A standard ANSI “C” 80515-application programming
interface library is available to help reduce design cycle. Refer to the 73S12xxF Software User’s Guide.
1.3.2 Memory Organization
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three
memory areas: Program memory (Flash), external data memory (XRAM), and internal data memory
(IRAM). Data bus address space is allocated to on-chip memory as shown Table 2.
Table 2: MPU Data Memory Map
Address
(hex)
Memory
Technology
Memory Size
(bytes)
Memory Type
Typical Usage
0000-FFFF
Flash Memory
Non-volatile
Program and non-volatile
data
64KB
0000-07FF
FC00-FFFF
Static RAM
Volatile
Volatile
MPU data XRAM
Peripheral control
2KB
1KB
External SFR
Note: The IRAM is part of the core and is addressed differently.
Rev. 1.2
11
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
