73S1217F Data Sheet
DS_1217F_002
Pin Name
Description
OFF_REQ
52
O
Figure 36 Digital output. If ON_OFF switch is closed (to ground) for de-
bounce duration and circuit is “on,” OFF_REQ will go high
(Request to turn OFF). This output should be connected to
an interrupt pin to signal the CPU core that a request to shut
down power has been initiated. The firmware can then
perform all of its shut down housekeeping duties before
shutting down VDD.
TBUS(3:0)0
50
46
44
41
IO
Trace bus signals for ICE.
1
2
3
RXTX
ERST
ISBR
43
38
3
IO
IO
IO
I
ICE control.
ICE control.
ICE control.
ICE control.
TCLK
ANA_IN
39
15
AI
Figure 41 Analog input pin. This signal goes to a programmable
comparator and is used to sense the value of an external
voltage.
LED0
SEC
4
2
IO
I
Figure 39 Special output driver, programmable pull-down current to
drive LED. May also be used as an input.
Figure 40 Input pin for use in programming security fuse. It should be
connected to ground when not in use.
TEST
VDD
51
DI
Figure 40 Test pin, should be connected to ground.
68
28
40
PSO
VDD supply output pin. A 0.1μF capacitor is recommended at
each VDD pin.
GND
9
GND
I
General ground supply pins for all IO and logic circuits.
25
42
67
RESET
1
Figure 35 Reset input, positive assertion. Resets logic and registers to
default condition. Note: to insure proper reset operation after
VDD is turned on by application of VBUS power or activation of
the ON/OFF switch, external reset circuitry must generate a
proper reset signal to the 73S1217F. This can be
accomplished via a simple RC network.
* See the figures in the Equivalent Circuits section.
10
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
