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73S1217F-IMR/F 参数 Datasheet PDF下载

73S1217F-IMR/F图片预览
型号: 73S1217F-IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 总线供电80515的系统级芯片, USB , ISO 7816 / EMV ,密码键盘和更多 [Bus-Powered 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More]
分类和应用: 多功能外围设备微控制器和处理器时钟
文件页数/大小: 140 页 / 1066 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_1217F_002  
73S1217F Data Sheet  
Table 3: Flash Special Function Registers  
Description  
Register  
SFR  
R/W  
Address  
ERASE  
0x94  
W
This register is used to initiate either the Flash Mass Erase cycle or the  
Flash Page Erase cycle. Specific patterns are expected for ERASE in  
order to initiate the appropriate Erase cycle (default = 0x00).  
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write  
to PGADDR @ SFR 0xB7.  
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write  
to FLSH_MEEN @ SFR 0xB2 and the debug port must be  
enabled.  
Any other pattern written to ERASE will have no effect.  
PGADDR  
FLSHCTL  
0xB7  
0xB2  
R/W Flash Page Erase Address register containing the flash memory page  
address (page 0 through 127) that will be erased during the Page Erase  
cycle (default = 0x00). Note: the page address is shifted left by one bit  
(see detailed description above).  
Must be re-written for each new Page Erase cycle.  
R/W Bit 0 (FLSH_PWE): Program Write Enable:  
0 – MOVX commands refer to XRAM Space, normal operation (default).  
1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.  
This bit is automatically reset after each byte written to flash. Writes to  
this bit are inhibited when interrupts are enabled.  
W
Bit 1 (FLSH_MEEN): Mass Erase Enable:  
0 – Mass Erase disabled (default).  
1 – Mass Erase enabled.  
Must be re-written for each new Mass Erase cycle.  
R/W Bit 6 (SECURE):  
Enables security provisions that prevent external reading of flash  
memory and CE program RAM. This bit is reset on chip reset and may  
only be set. Attempts to write zero are ignored.  
Internal Data Memory: The internal data memory provides 256 bytes (0x00 to 0xFF) of data memory.  
The internal data memory address is always one byte wide and can be accessed by either direct or  
indirect addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is  
available only by direct addressing. Indirect addressing accesses the upper 128 bytes of Internal  
RAM.  
The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form  
four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select which  
bank is in use. The next 16 bytes form a block of bit-addressable memory space at bit addresses 0x00-  
0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. Table 4  
shows the internal data memory map.  
Rev. 1.2  
13  
 
 
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