DS_1215F_003
73S1215F Data Sheet
VCC Stable Timer Register (VccTmr): 0xFE04 Å 0x0F
A programmable timer is provided to set the time from activation start (setting the VCCSEL.1 and
VCCSEL.0 bits to non-zero) to when VCC_OK is evaluated. VCC_OK must be true at the end of this
timers programmed interval (tto in Figure 17) in order for the activation sequence to continue. If VCC_OK
is not true and the end of the interval (tto), the Card Event interrupt will be set, and a deactivation
sequence shall begin including clearing of the VCCSEL bits.
Table 85: The VccTmr Register
MSB
LSB
OFFTMR.3 OFFTMR.2 OFFTMR.1 OFFTMR.0 VCCTMR.3 VCCTMR.2 VCCTMR.1 VCCTMR.0
Bit
Symbol
Function
VccTmr.7 OFFTMR.3 VCC Off Timer – The bits set the delay (in number of ETUs) for
deactivation after the VCCSEL.1 and VCC SEL.0 have been set
to 0. The time value is a count of the 32768Hz clock and is given
by tto = OFFTMR(7:4) * 30.5μs. This delay does not affect
emergency deactivations due to VDD Fault or card events. A
VccTmr.6 OFFTMR.2
VccTmr.5 OFFTMR.1
VccTmr.4 OFFTMR.0
value of 0000 results in no additional delay.
VccTmr.3 VCCTMR.3 VCC Timer – VCCOK must be true at the time set by the value in
these bits in order for the activation sequence to continue. If not,
the VCCSEL bits will be cleared. The time value is a count of the
32768Hz clock and is given by tto = VCCTMR(3:0) * 30.5μs. A
value of 0000 results in no timeout, not zero time, and activation
VccTmr.2 VCCTMR.2
VccTmr.1 VCCTMR.1
VccTmr.0 VCCTMR.0
requires that RDYST is set and RDY goes high.
Rev. 1.4
91
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
