DS_1215F_003
73S1215F Data Sheet
I2C Secondary Read Data Register (SRDR): 0XFF84 Å 0x00
Table 67: The SRDR Register
MSB
LSB
SRDR.0
SRDR.7
SRDR.6
SRDR.5
SRDR.4
SRDR.3
SRDR.2
SRDR.1
Bit
Function
SRDR.7
SRDR.6
SRDR.5
SRDR.4
SRDR.3
SRDR.2
SRDR.1
SRDR.0
Second Data byte to be read from the I2C slave device if bit 0 (I2CLEN) of the Control
and Status register (CSR) is set = 1.
I2C Control and Status Register (CSR): 0xFF85 Å 0x00
Table 68: The CSR Register
MSB
LSB
–
–
–
–
–
AKERR I2CST I2CLEN
Bit
Symbol
Function
CSR.7
CSR.6
CSR.5
CSR.4
CSR.3
–
–
–
–
–
Set to 1 if acknowledge bit from Slave Device is not 0. Automatically reset
when the new bus transaction is started.
CSR.2
AKERR
Write a 1 to start I2C transaction. Automatically reset to 0 when the bus
transaction is done. This bit should be treated as a “busy” indicator on
reading. If it is high, the serial read/write operations are not completed and
no new address or data should be written.
CSR.1
CSR.0
I2CST
I2CLEN
Set to 1 for 2-byte read or write operations. Set to 0 for 1-byte operations.
Rev. 1.4
63
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
