DS_1215F_003
73S1215F Data Sheet
Figure 10 shows the timing of the I2C write mode.
Transfer length
(CSR bit0)
Start I2C
(CSR bit1)
I2C_Interrupt
SDA
Device Address
Write Data [7:0
MSB LSB
[7:0]
MSB
LSB
SCL
1-7
8
9
10-17
18
ACK bit
ACK bit
START
STOP
condition
condition
Transfer length
(CSR bit0)
Start I2C
(CSR bit1)
I2C_Interrupt
SDA
Device Address
[7:0]
Secondary Write
Data [7:0]
Write Data [7:0]
MSB
LSB
MSB
LSB
MSB
LSB
SCL
1-7
8
9
10-17
18
19-26
27
ACK bit
ACK bit
ACK bit
STOP
START
condition
condition
Figure 10: I2C Write Mode Operation
1.7.11.2 I2C Read Sequence
To read data on the I2C Master Bus from a slave device, the 80515 has to program the following registers
in this sequence:
1. Write slave device address to the Device Address register (DAR). The data contains 7 bits device
address and 1 bit of op-code. The op-code bit should be written with a 1.
2. Write control data to the Control and Status register (CSR). Write a 1 to bit 1 to start I2C Master Bus.
Also write a 1 to bit 0 if the Secondary Read Data (SRDR) register is to be captured from the I2C
Slave device.
3. Wait for I2C interrupt to be asserted. It indicates that the read operation on the I2C bus is done.
Refer to information about the INT6Ctl, IEN1 and IRCON registers for masking and flag operation.
4. Read data from the Read Data register (RDR).
5. Read data from Secondary Read Data register (SRDR) if bit 0 of Control and Status register (CSR) is
written with a 1.
Rev. 1.4
59
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
