73S1215F Data Sheet
DS_1215F_003
PDMUX
(FF94h:bit7)
USR0
USR1
USR[7:0] Control
MPU
INT0
USR2
USR3
USR4
USR5
USR6
USR7
0
1
USRxINTSrc set to
4(ext INT0 high)
or
6(ext INT0 low)
INT4
INT5
CE
TC
9 BIT CNTR
CLR
RESETB
PWRDN
(FFF1h:bit7)
D
Q
PWRDN_analog
CLR
TC
CE
RESETB
5 BIT CNTR
Notes:
CLR
1. The counters are clocked by the MPUCLK
2. TC - Terminal count (high at overflow)
3. CE - Count enable
RESETB
Figure 6: Detail of Power Down Interrupt Logic
text
t0
PWRDN BIT
t1
PWRDN SIG
EXT. EVENT
t4
t6
INT0 to MPU
MPU STOP
t7
t2
ANALOG Enable
t3
t5
PLL CLOCKS
t0: MPU sets PWRDN bit
t1: 32 MPU clock cycles after t0, the PWRDN SIG is asserted, turning all analog functions OFF.
t2: MPU executes STOP instruction, must be done prior to t1.
t3: Analog functions go to OFF condition. No Vref, PLL/VCO, Ibias, etc.
text: An external event (RTC, Keypad, Card event, USB) occurs.
t4: PWRDN bit and PWRDN signal are cleared by external event.
t5: High-speed oscillator/PLL/VCO operating.
t6: After 512 MPU clock cycles, INT0 to MPU is asserted.
t7: INT0 causes MPU to exit STOP condition.
Figure 7: Power Down Sequencing
28
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
